search for: nv84_fence_cr

...ize_nc, > (nvbo->tile_flags >> 8) & 0x3ff, &node); > diff --git a/drm/nouveau/nv84_fence.c b/drm/nouveau/nv84_fence.c > index bf429ca..952bc48 100644 > --- a/drm/nouveau/nv84_fence.c > +++ b/drm/nouveau/nv84_fence.c > @@ -215,6 +215,7 @@ nv84_fence_create(struct nouveau_drm *drm) > { > struct nvkm_fifo *pfifo = nvxx_fifo(&drm->device); > struct nv84_fence_priv *priv; > + u32 domain; > int ret; > > priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); > @@ -231,10 +232,12...

...gt;page_alignment << PAGE_SHIFT, size_nc, (nvbo->tile_flags >> 8) & 0x3ff, &node); diff --git a/drm/nouveau/nv84_fence.c b/drm/nouveau/nv84_fence.c index bf429cabbaa8..b981f85de888 100644 --- a/drm/nouveau/nv84_fence.c +++ b/drm/nouveau/nv84_fence.c @@ -215,6 +215,7 @@ nv84_fence_create(struct nouveau_drm *drm) { struct nvkm_fifo *pfifo = nvxx_fifo(&drm->device); struct nv84_fence_priv *priv; + u32 domain; int ret; priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); @@ -231,10 +232,17 @@ nv84_fence_create(struct nouveau_drm *drm) priv->base.contex...

...mem->page_alignment << PAGE_SHIFT, size_nc, (nvbo->tile_flags >> 8) & 0x3ff, &node); diff --git a/drm/nouveau/nv84_fence.c b/drm/nouveau/nv84_fence.c index bf429ca..952bc48 100644 --- a/drm/nouveau/nv84_fence.c +++ b/drm/nouveau/nv84_fence.c @@ -215,6 +215,7 @@ nv84_fence_create(struct nouveau_drm *drm) { struct nvkm_fifo *pfifo = nvxx_fifo(&drm->device); struct nv84_fence_priv *priv; + u32 domain; int ret; priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); @@ -231,10 +232,12 @@ nv84_fence_create(struct nouveau_drm *drm) priv->base.contex...

...mem->page_alignment << PAGE_SHIFT, size_nc, (nvbo->tile_flags >> 8) & 0x3ff, &node); diff --git a/drm/nouveau/nv84_fence.c b/drm/nouveau/nv84_fence.c index bf429ca..b981f85 100644 --- a/drm/nouveau/nv84_fence.c +++ b/drm/nouveau/nv84_fence.c @@ -215,6 +215,7 @@ nv84_fence_create(struct nouveau_drm *drm) { struct nvkm_fifo *pfifo = nvxx_fifo(&drm->device); struct nv84_fence_priv *priv; + u32 domain; int ret; priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); @@ -231,10 +232,17 @@ nv84_fence_create(struct nouveau_drm *drm) priv->base.contex...

...aw_write_lock+0x2f/0x40 [ 30.457006] drm_vma_offset_add+0x1c/0x60 [drm] [ 30.457013] ttm_bo_init_reserved+0x28b/0x460 [ttm] [ 30.457020] ttm_bo_init+0x57/0x110 [ttm] [ 30.457066] nouveau_bo_init+0xb0/0xc0 [nouveau] [ 30.457108] nouveau_bo_new+0x4d/0x60 [nouveau] [ 30.457145] nv84_fence_create+0xb9/0x130 [nouveau] [ 30.457180] nvc0_fence_create+0xe/0x47 [nouveau] [ 30.457221] nouveau_drm_device_init+0x3d9/0x800 [nouveau] [ 30.457262] nouveau_drm_probe+0xfb/0x200 [nouveau] [ 30.457268] local_pci_probe+0x42/0x90 [ 30.457272] pci_device_probe+0xe7/0x1a0 [ 30.457276...

...2 nv10_fence_read(struct nouveau_channel *); void nv10_fence_context_del(struct nouveau_channel *); void nv10_fence_destroy(struct nouveau_drm *); int nv10_fence_create(struct nouveau_drm *); +void nv17_fence_resume(struct nouveau_drm *drm); int nv50_fence_create(struct nouveau_drm *); int nv84_fence_create(struct nouveau_drm *); diff --git a/drivers/gpu/drm/nouveau/nv10_fence.c b/drivers/gpu/drm/nouveau/nv10_fence.c index 7ae7f97..0619c02 100644 --- a/drivers/gpu/drm/nouveau/nv10_fence.c +++ b/drivers/gpu/drm/nouveau/nv10_fence.c @@ -162,6 +162,13 @@ nv10_fence_destroy(struct nouveau_drm *drm)...

...c44 which actually introduces the nv84+ fence mechanism. This had actually previously occurred to me, but a quick thing to try out is to switch to the nv17 fence and see what happens. You can do this by editing the logic in drivers/gpu/drm/nouveau/nouveau_drm.c:nouveau_accel_init, and just replace nv84_fence_create with nv50_fence_create (which will make a nv50+ appropriate nv17 fence impl). -- You are receiving this mail because: You are the assignee for the bug. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/nouveau/attachments...

..., and I simply don't have a spec file which properly builds such a kernel from git, so I need to export the git snapshot to a tarball. In case you have such an RHEL6/OL6 spec file (or know where to get one from), please let me know... I'm just in the process of trying whether moving from nv84_fence_create to nv50_fence_create will make a difference with 3.6.11 and will report back later. BR, Andreas -- You are receiving this mail because: You are the assignee for the bug. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/...

...t; (nvbo->tile_flags >> 8) & 0x3ff, &node); > diff --git a/drm/nouveau/nv84_fence.c b/drm/nouveau/nv84_fence.c > index bf429cabbaa8..b981f85de888 100644 > --- a/drm/nouveau/nv84_fence.c > +++ b/drm/nouveau/nv84_fence.c > @@ -215,6 +215,7 @@ nv84_fence_create(struct nouveau_drm *drm) > { > struct nvkm_fifo *pfifo = nvxx_fifo(&drm->device); > struct nv84_fence_priv *priv; > + u32 domain; > int ret; > > priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); > @@ -231,10 +232,17...

...nouveau_drm *d else if (device->chipset < 0x17) ret = nv10_fence_create(drm); else if (device->card_type < NV_50) ret = nv17_fence_create(drm); else if (device->chipset < 0x84) ret = nv50_fence_create(drm); - else if (device->card_type < NV_C0) ret = nv84_fence_create(drm); + else if (device->card_type < NV_C0) ret = nv50_fence_create(drm); else ret = nvc0_fence_create(drm); if (ret) { NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret); but the result is that after the GUI log...

A series I have waited too long to submit, and the recent refactoring made me pay the price of my perfectionism, so here are the features that are at least completed Patches 1-3 make the presence of a RAM device optional, and remove GK20A's dummy RAM driver we were using so far. On chips using shared memory, such a device can confuse the driver into moving objects where there is no need to,

On Fri, 23 Oct 2020 14:07:13 +0200 Mike Galbraith wrote: > On Fri, 2020-10-23 at 11:01 +0200, Sebastian Andrzej Siewior wrote: > > On 2020-10-22 07:28:20 [+0200], Mike Galbraith wrote: > > > I've only as yet seen nouveau lockdep gripage when firing up one of my > > > full distro KVM's. > > > > Could you please check !RT with the `threadirqs'

Thanks Ilia for the v2 review! Here is the v3 of this IOMMU support for GK20A series. Changes since v2: - Cleaner changes for ltc - Fixed typos in gk20a instmem IOMMU comments Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into nouveau_display.c and nv84_fence.c. Original cover letter: Patches 1-3 make the presence of a RAM device optional, and remove

It has been a couple of months since v4 - apologies for this. v4 has not received many comments, but this version addresses them and makes a new attempt at pushing the critical bit for GK20A and Nouveau on ARM in general. As a reminder, this series addresses the memory coherency issue that we are seeing on ARM platforms. Contrary to x86 which invalidates the PCI caches whenever a write is made by

...eau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM, false); if (!ret) { diff --git a/drivers/gpu/drm/nouveau/nv84_fence.c b/drivers/gpu/drm/nouveau/nv84_fence.c index f07da00f285f..fecdb036521e 100644 --- a/drivers/gpu/drm/nouveau/nv84_fence.c +++ b/drivers/gpu/drm/nouveau/nv84_fence.c @@ -204,7 +204,7 @@ nv84_fence_create(struct nouveau_drm *drm) */ TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED; ret = nouveau_bo_new(&drm->client, 16 * drm->chan.nr, 0, - domain, 0, 0, NULL, NULL, &priv->bo); + domain, 0, 0, NULL, NULL, false, &priv->bo); if (ret == 0) { ret = nouvea...

...veau_fifo(device) /*XXX*/) return; @@ -150,7 +150,9 @@ nouveau_accel_init(struct nouveau_drm *drm) else if (device->card_type < NV_50) ret = nv17_fence_create(drm); else if (device->chipset < 0x84) ret = nv50_fence_create(drm); else if (device->card_type < NV_C0) ret = nv84_fence_create(drm); +#ifdef CONFIG_DRM_NOUVEAU_NVC0 else ret = nvc0_fence_create(drm); +#endif if (ret) { NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret); nouveau_accel_fini(drm); diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.h b/drivers...

Changes since v3: - Use a single dma_attr for all DMA-API allocations in instmem instead of one per allocation - Use device.info.ram_size instead of pfb->ram to check whether VRAM is present outside of nvkm Changes since v2: - Cleaner changes for ltc - Fixed typos in gk20a instmem IOMMU comments Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into

Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into nouveau_display.c and nv84_fence.c. Original cover letter: Patches 1-3 make the presence of a RAM device optional, and remove GK20A's dummy RAM driver we were using so far. On chips using shared memory, such a device can confuse the driver into moving objects where there is no need to, and can trick

...= nv84_fence_emit32; fctx->base.sync32 = nv84_fence_sync32; + fctx->base.sequence = nv84_fence_read(chan); + fctx->base.context = priv->base.context_base + fifo->chid; ret = nouveau_bo_vma_add(priv->bo, client->vm, &fctx->vma); if (ret == 0) { @@ -239,7 +241,8 @@ nv84_fence_create(struct nouveau_drm *drm) priv->base.context_new = nv84_fence_context_new; priv->base.context_del = nv84_fence_context_del; - init_waitqueue_head(&priv->base.waiting); + priv->base.contexts = pfifo->max + 1; + priv->base.context_base = fence_context_alloc(priv->bas...

...> @@ -150,7 +150,9 @@ nouveau_accel_init(struct nouveau_drm *drm) > else if (device->card_type < NV_50) ret = nv17_fence_create(drm); > else if (device->chipset < 0x84) ret = nv50_fence_create(drm); > else if (device->card_type < NV_C0) ret = nv84_fence_create(drm); > +#ifdef CONFIG_DRM_NOUVEAU_NVC0 > else ret = nvc0_fence_create(drm); > +#endif > if (ret) { > NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret); > nouveau_accel_fini(...