Displaying 7 results from an estimated 7 matches for "nv50tic_0_0_fmt_8_8".
2016 Oct 17
2
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
...his seems wrong. Why do you shift width/height here?
> + NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
> NV50TIC_0_0_MAPB_C0 | NV50TIC_0_0_TYPEB_UNORM |
> NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
> NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
> NV50TIC_0_0_FMT_8_8);
> - PUSH_DATA (push, ((src->offset + uv)));
> - PUSH_DATA (push, ((src->offset + uv) >> 32) | mode);
> - PUSH_DATA (push, 0x00300000);
> - PUSH_DATA (push, width >> 1);
> - PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | (height >> 1));
> - PUSH_D...
2016 Oct 16
0
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
...PEA_UNORM |
+ PUSH_TIC(push, src, uv, width >> 1, height >> 1, 0,
+ NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPB_C0 | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
NV50TIC_0_0_FMT_8_8);
- PUSH_DATA (push, ((src->offset + uv)));
- PUSH_DATA (push, ((src->offset + uv) >> 32) | mode);
- PUSH_DATA (push, 0x00300000);
- PUSH_DATA (push, width >> 1);
- PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | (height >> 1));
- PUSH_DATA (push, 0x03000000);
- PUSH...
2016 Oct 27
0
[PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
...PEA_UNORM |
+ PUSH_TIC(push, src, uv, width >> 1, height >> 1, 0,
+ NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPB_C0 | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
NV50TIC_0_0_FMT_8_8);
- PUSH_DATA (push, ((src->offset + uv)));
- PUSH_DATA (push, ((src->offset + uv) >> 32) | mode);
- PUSH_DATA (push, 0x00300000);
- PUSH_DATA (push, width >> 1);
- PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | (height >> 1));
- PUSH_DATA (push, 0x03000000);
- PUSH...
2016 Oct 17
0
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
...0_TYPEA_UNORM |
>> NV50TIC_0_0_MAPB_C0 | NV50TIC_0_0_TYPEB_UNORM |
>> NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
>> NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
>> NV50TIC_0_0_FMT_8_8);
>> - PUSH_DATA (push, ((src->offset + uv)));
>> - PUSH_DATA (push, ((src->offset + uv) >> 32) | mode);
>> - PUSH_DATA (push, 0x00300000);
>> - PUSH_DATA (push, width >> 1);
>> - PUSH_DATA (push, (1 << NV50TIC_0_5_...
2016 Oct 27
2
[PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
...ush, src, uv, width >> 1, height >> 1, 0,
> + NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
> NV50TIC_0_0_MAPB_C0 | NV50TIC_0_0_TYPEB_UNORM |
> NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
> NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
> NV50TIC_0_0_FMT_8_8);
> - PUSH_DATA (push, ((src->offset + uv)));
> - PUSH_DATA (push, ((src->offset + uv) >> 32) | mode);
> - PUSH_DATA (push, 0x00300000);
> - PUSH_DATA (push, width >> 1);
> - PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | (height >> 1));
> - PUSH_D...
2016 Oct 16
10
[PATCH 1/5] hwdefs: update nvc0_3d, add gm107_texture for new TIC format
These are copied directly from the mesa repository.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
src/hwdefs/gm107_texture.xml.h | 365 +++++++++++++++++
src/hwdefs/nvc0_3d.xml.h | 867 +++++++++++++++++++++++++----------------
2 files changed, 892 insertions(+), 340 deletions(-)
create mode 100644 src/hwdefs/gm107_texture.xml.h
diff --git
2016 Oct 27
11
[PATCH v2 0/7] Add Maxwell support
I believe I've addressed all the feedback from the first time around, and
also made fixes necessary for GM20x based on testing results. I believe
now it should actually work for all GM10x and GM20x. Further, GP10x should
be very easy to add, but without someone to actually test I didn't want to
claim support for it.
Ilia Mirkin (7):
exa: add GM10x acceleration support
hwdefs: update