Displaying 11 results from an estimated 11 matches for "nv50_reg".
2009 Jun 21
0
[PATCH] nv50: support for SLE, SNE, SEQ, SGT
...), 38 deletions(-)
diff --git a/src/gallium/drivers/nv50/nv50_program.c b/src/gallium/drivers/nv50/nv50_program.c
index 16bf2f1..75c5cea 100644
--- a/src/gallium/drivers/nv50/nv50_program.c
+++ b/src/gallium/drivers/nv50/nv50_program.c
@@ -810,7 +810,11 @@ emit_precossin(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
#define CVTOP_TRUNC 0x07
#define CVTOP_SAT 0x08
#define CVTOP_ABS 0x10
+#define CVTOP_ABSRN 0x11
+/* 0x04 == 32 bit */
+/* 0x40 == dst is float */
+/* 0x80 == src is float */
#define CVT_F32_F32 0xc4
#define CVT_F32_S32 0x44
#define CVT_F32_U32 0x64
@@ -819,8 +82...
2009 Sep 10
0
[PATCH 06/13] nv50: handle SEQ, SGT, SLE, SNE opcodes
...+), 30 deletions(-)
diff --git a/src/gallium/drivers/nv50/nv50_program.c b/src/gallium/drivers/nv50/nv50_program.c
index e7beb26..381e396 100644
--- a/src/gallium/drivers/nv50/nv50_program.c
+++ b/src/gallium/drivers/nv50/nv50_program.c
@@ -790,6 +790,9 @@ emit_precossin(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
#define CVTOP_SAT 0x08
#define CVTOP_ABS 0x10
+/* 0x04 == 32 bit */
+/* 0x40 == dst is float */
+/* 0x80 == src is float */
#define CVT_F32_F32 0xc4
#define CVT_F32_S32 0x44
#define CVT_F32_U32 0x64
@@ -799,7 +802,7 @@ emit_precossin(struct nv50_pc *pc, struct nv5...
2009 May 06
2
nv50: shader generation patches
Hi ! I've been trying to improve NV50 shader generation a bit the last couple of weeks, so here is
what I've produced. I don't know if it's usable for you or just a pile of horrible hacks, but at
least it makes some mesa demos render more correcly, p.e. the teapot (aside from mip-mapping issues
of the floor texture), arbfplight, and I think the gears also didn't appear as they
2009 Jun 21
0
[PATCH] nv50: initial support for IF, ELSE, ENDIF insns
...1 +
2 files changed, 132 insertions(+), 31 deletions(-)
diff --git a/src/gallium/drivers/nv50/nv50_program.c b/src/gallium/drivers/nv50/nv50_program.c
index 5594560..16bf2f1 100644
--- a/src/gallium/drivers/nv50/nv50_program.c
+++ b/src/gallium/drivers/nv50/nv50_program.c
@@ -90,6 +90,8 @@ struct nv50_reg {
int acc; /* instruction where this reg is last read (first insn == 1) */
};
+#define MAX_IF_LEVEL 4 /* arbitrary value */
+
struct nv50_pc {
struct nv50_program *p;
@@ -119,11 +121,17 @@ struct nv50_pc {
struct nv50_reg r_hpos[4];
+ struct nv50_program_exec *if_cond;
+ struct nv50...
2009 Sep 12
0
[PATCH 09/13] nv50: move allocation of pc regs
Make use of tgsi_shader_info to determine how many nv50_regs
we need to allocate, if program uses KIL, or writes DEPR.
---
src/gallium/drivers/nv50/nv50_program.c | 284 ++++++++++++++-----------------
1 files changed, 129 insertions(+), 155 deletions(-)
diff --git a/src/gallium/drivers/nv50/nv50_program.c b/src/gallium/drivers/nv50/nv50_program.c
index...
2009 Jun 21
0
[PATCH] nv50: better insn generation
...00644
--- a/src/gallium/drivers/nv50/nv50_program.c
+++ b/src/gallium/drivers/nv50/nv50_program.c
@@ -1294,18 +1294,20 @@ static boolean
nv50_program_tx_insn(struct nv50_pc *pc, const union tgsi_full_token *tok)
{
const struct tgsi_full_instruction *inst = &tok->FullInstruction;
- struct nv50_reg *rdst[4], *dst[4], *src[3][4], *temp;
- unsigned mask, sat, unit;
+ struct nv50_reg *rdst[4], *dst[4], *src[3][4];
+ struct nv50_reg **pp_rtmp, *rtmp = NULL, *temp = NULL;
+ unsigned mask, sat, unit = 0;
boolean assimilate = FALSE;
- int i, c;
+ int i, c, nr_dst = 0;
mask = inst->FullDstRe...
2009 Sep 12
0
[PATCH 10/13] nv50: proper linkage between VP and FP
...0_program *p);
/* nv50_state_validate.c */
diff --git a/src/gallium/drivers/nv50/nv50_program.c b/src/gallium/drivers/nv50/nv50_program.c
index c8157f1..feb1504 100644
--- a/src/gallium/drivers/nv50/nv50_program.c
+++ b/src/gallium/drivers/nv50/nv50_program.c
@@ -139,6 +139,14 @@ ctor_reg(struct nv50_reg *reg, unsigned type, int index, int hw)
reg->acc = 0;
}
+static INLINE unsigned
+popcnt4(uint32_t val)
+{
+ static const unsigned cnt[16]
+ = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
+ return cnt[val & 0xf];
+}
+
static void
alloc_reg(struct nv50_pc *pc, struct nv50_reg *re...
2009 Sep 10
0
[PATCH 01/13] nv50: extend insn src mask function
...TGSI_TEXTURE_2D:
+ mask &= 0xb;
+ break;
+ default:
+ break;
+ }
+ }
+ return mask;
+ case TGSI_OPCODE_XPD:
+ x = 0;
+ if (mask & 1) x |= 0x6;
+ if (mask & 2) x |= 0x5;
+ if (mask & 4) x |= 0x3;
+ return x;
+ default:
+ break;
+ }
+
+ return mask;
+}
+
static struct nv50_reg *
tgsi_dst(struct nv50_pc *pc, int c, const struct tgsi_full_dst_register *dst)
{
@@ -1310,13 +1374,18 @@ nv50_program_tx_insn(struct nv50_pc *pc, const union tgsi_full_token *tok)
for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *fs = &ins...
2009 Jun 21
0
[PATCH] nv50: update comments
...isabled)
+ *
+ * 1988 = 0xMMIInnii
+ * MM = bitmask to un-mask masked VP/GP outputs (i.e. HPOS, generic ?)
+ * nn = map index of first non-masked output, where to put front color
+ * II = count of non-masked interpolants
+ * ii = almost always equal to II (except if II -> 00, why ?)
*/
struct nv50_reg {
enum {
@@ -2705,31 +2720,6 @@ program_del_linkage(struct nv50_linkage *ln)
FREE(ln);
}
-/*
- * 1510 = bitmask to enable clipping planes
- * 1688 = two-sided lighting enable
- * 16ac = entry count of mapping table at [16bc]
- * 16b0 = count of temporaries used in VP
- *
- * 1904 = 0x01CCBBF...
2009 Sep 10
0
[PATCH 02/13] nv50: add functions for swizzle resolution
...order, not component */
+ return unsafe;
+}
+
+/* Select a suitable dst register for broadcasting scalar results,
+ * or return NULL if we have to allocate an extra TEMP.
+ *
+ * If e.g. only 1 component is written, we may also emit the final
+ * result to a write-only register.
+ */
+static struct nv50_reg *
+tgsi_broadcast_dst(struct nv50_pc *pc,
+ const struct tgsi_full_dst_register *fd, unsigned mask)
+{
+ if (fd->DstRegister.File == TGSI_FILE_TEMPORARY) {
+ int c = ffs(~mask & fd->DstRegister.WriteMask);
+ if (c)
+ return tgsi_dst(pc, c - 1, fd);
+ } else {
+ int c = ffs(fd->...
2009 Jun 24
0
[PATCH] nv50: fix previous patches
...rently it goes after all color outputs)
+ * FP results: can DEPR output be mapped to another register ?
+ * (currently it's index is that of the last color's register + 1)
*
* 1298 = 0x00000004; or 0x00000005 if DEPR is written
*
@@ -444,7 +445,7 @@ set_immd(struct nv50_pc *pc, struct nv50_reg *imm, struct nv50_program_exec *e)
#define INTERP_LINEAR 0
-#define INTERP_FLAT 1
+#define INTERP_FLAT 1
#define INTERP_PERSPECTIVE 2
#define INTERP_CENTROID 4
@@ -1852,6 +1853,10 @@ prep_inspect_insn(struct nv50_pc *pc, const union tgsi_full_token *tok,
dst = &insn->FullDstR...