Displaying 3 results from an estimated 3 matches for "nv50_pgraph_status".
Did you mean:
nv10_pgraph_tstatus
2012 Nov 06
1
[PATCH] drm/nv50: decode PGRAPH status registers on TLB flush fail
...ouveau/core/engine/graph/nv50.c
index ab3b9dc..5f1adca 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
@@ -184,6 +184,62 @@ nv50_graph_tlb_flush(struct nouveau_engine *engine)
return 0;
}
+static const struct nouveau_bitfield nv50_pgraph_status[] = {
+ { 0x00000001, "BUSY" }, /* set when any bit is set */
+ { 0x00000002, "DISPATCH" },
+ { 0x00000004, "UNK2" },
+ { 0x00000008, "UNK3" },
+ { 0x00000010, "UNK4" },
+ { 0x00000020, "UNK5" },
+ { 0x00000040, "M2MF" },
+ { 0x0...
2012 Aug 19
1
[PATCH 01/10] drm/nv50: decode PGRAPH status registers on TLB flush fail
.../drm/nouveau/core/engine/graph/nv50.c
index c93b525..f60aec9 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
@@ -184,6 +184,62 @@ nv50_graph_tlb_flush(struct nouveau_engine *engine)
return 0;
}
+static struct nouveau_bitfield nv50_pgraph_status[] = {
+ { 1<<0, "BUSY" }, /* set when any bit is set */
+ { 1<<1, "DISPATCH" },
+ { 1<<2, "UNK2" },
+ { 1<<3, "UNK3" },
+ { 1<<4, "UNK4" },
+ { 1<<5, "UNK5" },
+ { 1<<6, "M2MF" },
+ { 1&l...
2014 Feb 05
0
[PATCH] drm/nv50/graph: update status enum names
.../drivers/gpu/drm/nouveau/core/engine/graph/nv50.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
index 30ed19c..6da473c 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
@@ -197,34 +197,35 @@ static const struct nouveau_bitfield nv50_pgraph_status[] = {
{ 0x00000080, "UNK7" },
{ 0x00000100, "CTXPROG" },
{ 0x00000200, "VFETCH" },
- { 0x00000400, "CCACHE_UNK4" },
- { 0x00000800, "STRMOUT_GSCHED_UNK5" },
- { 0x00001000, "UNK14XX" },
- { 0x00002000, "UNK24XX_CSCHED" },
-...