Displaying 6 results from an estimated 6 matches for "nv50_ir_subop_bfind_samt".
2014 May 29
1
[PATCH 4/4] nvc0/ir: Handle OP_BFIND when folding constant expressions
.....a56756c 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -556,6 +556,20 @@ ConstantFolding::expr(Instruction *i,
}
break;
}
+ case OP_BFIND: {
+ int shift = 0;
+ if (i->subOp == NV50_IR_SUBOP_BFIND_SAMT)
+ shift = 32 - (b->data.u32 & 0xff);
+ switch (i->dType) {
+ case TYPE_S32:
+ res.data.s32 = util_last_bit_signed(a->data.s32 >> shift)- 1; break;
+ case TYPE_U32:
+ res.data.u32 = util_last_bit(a->data.u32 >> shift) -1; break;
+...
2014 Jun 03
8
[PATCH v2 0/4] Constant folding of new Instructions
And another try for constant folding of Instructions for nvc0.
Please Review this!
Thanks,
Tobias Klausmann
Tobias Klausmann (4):
nvc0/ir: clear subop when folding constant expressions
nvc0/ir: Handle reverse subop for OP_EXTBF when folding constant
expressions
nvc0/ir: Handle OP_BFIND when folding constant expressions
nvc0/ir: Handle OP_POPCNT when folding constant expressions
2014 Jun 03
0
[PATCH v2 3/4] nvc0/ir: Handle OP_BFIND when folding constant expressions
...IND: {
+ int32_t res;
+ switch (i->dType) {
+ case TYPE_S32:
+ res = util_last_bit_signed(imm0.reg.data.s32) - 1; break;
+ case TYPE_U32:
+ res = util_last_bit(imm0.reg.data.u32) -1; break;
+ default:
+ return;
+ }
+ if ((i->subOp == NV50_IR_SUBOP_BFIND_SAMT) && (res >= 0))
+ res = 31 - res;
+ i->setSrc(0, new_ImmediateValue(i->bb->getProgram(), (uint32_t)res));
+ i->setSrc(1, NULL);
+ i->op = OP_MOV;
+ i->subOp = 0;
+ break;
+ }
default:
return;
}
--
1.8.4.5
2014 May 29
4
Add constant folding for new opcodes
Hi,
please review the following 4 patches:
1b1cfc6 nvc0/ir: Handle OP_BFIND when folding constant expressions
d2d2727 nvc0/ir: Handle OP_POPCNT when folding constant expressions
86a1ee6 nvc0/ir: Handle reverse subop for OP_EXTBF when folding constant
expressions
84563bf nvc0/ir: clear subop when folding constant expressions
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 39
2014 Jun 03
6
[PATCH v3 0/4] Constant folding of new Instructions
Yet another try for constant folding of Instructions for nvc0.
Please Review this again! (Hopefully the last time ;-) )
Tobias Klausmann (4):
nvc0/ir: clear subop when folding constant expressions
nvc0/ir: Handle reverse subop for OP_EXTBF when folding constant
expressions
nvc0/ir: Handle OP_BFIND when folding constant expressions
nvc0/ir: Handle OP_POPCNT when folding constant
2015 Feb 20
10
[PATCH 01/11] nvc0/ir: add emission of dadd/dmul/dmad opcodes, fix minmax
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
.../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 66 +++++++++++++++++++++-
1 file changed, 63 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index dfb093c..e38a3b8 100644
---