search for: nv50_fb_init

...) { + dma_unmap_page(nv_device_base(device), priv->r100c18, PAGE_SIZE, + DMA_BIDIRECTIONAL); + __free_page(priv->r100c18_page); + } + + nv50_fb_dtor(object); +} + +int +nvaa_fb_init(struct nouveau_object *object) +{ + struct nvaa_fb_priv *priv = (void *)object; + int ret; + + ret = nv50_fb_init(object); + if (ret) + return ret; + + /* Enable NISO poller for various clients and set their associated + * read address, only for MCP77/78 and MCP79/7A. (fd#25701) + */ + nv_wr32(priv, 0x100c18, priv->r100c18 >> 8); + nv_mask(priv, 0x100c14, 0x00000000, 0x00000001); + nv_wr32(priv, 0x...

Signed-off-by: Pierre Moreau <pierre.morrow at free.fr> --- drm/nouveau_drm.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drm/nouveau_drm.c b/drm/nouveau_drm.c index afb93bb..ffa1e4f 100644 --- a/drm/nouveau_drm.c +++ b/drm/nouveau_drm.c @@ -61,9 +61,10 @@ MODULE_PARM_DESC(debug, "debug string to pass to driver core"); static char

...++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c index 4150b0d..5c84d13 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c @@ -289,6 +289,17 @@ nv50_fb_init(struct nouveau_object *object) if (ret) return ret; + /* Not a clue what this is exactly. Without enabling bit 1 of + * 100c14, system will lockup while initialising the card + * (#27501) + */ + if (nv_device(priv)->chipset == 0xac) { + if ((nv_rd32(priv, 0x100c14) & 0x00000002) =...

...) { + dma_unmap_page(nv_device_base(device), priv->r100c18, PAGE_SIZE, + DMA_BIDIRECTIONAL); + __free_page(priv->r100c18_page); + } + + nv50_fb_dtor(object); +} + +int +nvaa_fb_init(struct nouveau_object *object) +{ + struct nvaa_fb_priv *priv = (void *)object; + int ret; + + ret = nv50_fb_init(object); + if (ret) + return ret; + + /* Enable NISO poller for various clients and set their associated + * read address, only for MCP77/78 and MCP79/7A. (fd#25701) + */ + nv_wr32(priv, 0x100c18, priv->r100c18 >> 8); + nv_mask(priv, 0x100c14, 0x00000000, 0x00000001); + nv_wr32(priv, 0x...

...t; + __free_page(priv->r100c18_page); > + } > + > + nv50_fb_dtor(object); > +} > + > +int > +nvaa_fb_init(struct nouveau_object *object) > +{ > + struct nvaa_fb_priv *priv = (void *)object; > + int ret; > + > + ret = nv50_fb_init(object); > + if (ret) > + return ret; > + > + /* Enable NISO poller for various clients and set their associated > + * read address, only for MCP77/78 and MCP79/7A. (fd#25701) > + */ > + nv_wr32(priv, 0x100c18, priv->r100c18 >...

...tions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c index 1b5fb02eab2a..033ca0effb7e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c @@ -216,11 +216,30 @@ nv50_fb_init(struct nvkm_fb *base) struct nv50_fb *fb = nv50_fb(base); struct nvkm_device *device = fb->base.subdev.device; + if (!fb->r100c08) { + /* + * We are calling the DMA api way before the TTM layer sets the + * DMA mask based on the MMU subdev parameters. This means we + * are using...

...to specify them somewhere? Here is the patch so far, where priv->r100c08 is an address to an empty dma page: diff --git a/nvkm/subdev/fb/nv50.c b/nvkm/subdev/fb/nv50.c index 4150b0d..1a0a94e 100644 --- a/nvkm/subdev/fb/nv50.c +++ b/nvkm/subdev/fb/nv50.c @@ -295,6 +296,19 @@ nv50_fb_init(struct nouveau_object *object) */ nv_wr32(priv, 0x100c08, priv->r100c08 >> 8); + /* Enable NISO poller for various clients and set their associated + * read address, only for MCP77/78 and MCP79/7A. (fd#25701) + */ + if...

...tions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c index 1b5fb02eab2a..f029aaf01831 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c @@ -216,11 +216,23 @@ nv50_fb_init(struct nvkm_fb *base) struct nv50_fb *fb = nv50_fb(base); struct nvkm_device *device = fb->base.subdev.device; + if (!fb->r100c08) { + dma_addr_t addr = dma_map_page(device->dev, fb->r100c08_page, 0, + PAGE_SIZE, DMA_BIDIRECTIONAL); + if (!dma_mapping_error(device-&gt...

...--- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -930,6 +930,10 @@ extern void nv40_fb_takedown(struct drm_device *); extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t, uint32_t, uint32_t); +/* nv50_fb.c */ +extern int nv50_fb_init(struct drm_device *); +extern void nv50_fb_takedown(struct drm_device *); + /* nv04_fifo.c */ extern int nv04_fifo_init(struct drm_device *); extern void nv04_fifo_disable(struct drm_device *); diff --git a/drivers/gpu/drm/nouveau/nouveau_irq.c b/drivers/gpu/drm/nouveau/nouveau_irq.c index 9522...

This will fix races between generated ctxprogs and interrupt handler. Signed-off-by: Marcin Ko?cielnicki <koriakin at 0x04.net> --- drivers/gpu/drm/nouveau/nv50_grctx.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nv50_grctx.c b/drivers/gpu/drm/nouveau/nv50_grctx.c index d105fcd..9f909ab 100644 ---

...tions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c index 1b5fb02eab2a..f713cb3fe56c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c @@ -216,11 +216,33 @@ nv50_fb_init(struct nvkm_fb *base) struct nv50_fb *fb = nv50_fb(base); struct nvkm_device *device = fb->base.subdev.device; + if (!fb->r100c08) { + /* We are calling the DMA api way before the TTM layer sets the + * DMA mask based on the MMU subdev parameters. This means we + * are using the de...

This v4 is now a 3 piece series (since v4), after Alexandre pointed out that both GF 100 and NV50 are affected by the same issue, and that a related issue has been solved already for Tegra in commit 9d0394c6bed5 ("drm/nouveau/instmem/gk20a: set DMA mask early"). The issue that this series addresses is the fact that the Nouveau driver invokes the DMA API before setting the DMA mask. In

...tions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c index 1b5fb02eab2a..b2f05f733a53 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c @@ -216,11 +216,30 @@ nv50_fb_init(struct nvkm_fb *base) struct nv50_fb *fb = nv50_fb(base); struct nvkm_device *device = fb->base.subdev.device; + if (!fb->r100c08) { + /* + * We are calling the DMA api way before the TTM layer sets the + * DMA mask based on the MMU subdev parameters. This means we + * are using...

This is more or less simplified series of patches that bring power usage on my NV86 close to that of binary blob. Best regards, Maxim Levitsky

(Sending it to the correct Nvidia mailing list, sorry for the spam) Hi, When using acceleration with Nouveau on MacBook Pros with an 9400M (NVAC) card, a PFIFO interrupt 0x00400000 is thrown during the initialisation of that card (sometime after PFIFO and PGRAPH initialisation) and the laptop will lockup [1], forcing users to load Nouveau without acceleration. After some investigation, I found

This v4 is now a 3 piece series, after Alexandre pointed out that both GF 100 and NV50 are affected by the same issue, and that a related issue has been solved already for Tegra in commit 9d0394c6bed5 ("drm/nouveau/instmem/gk20a: set DMA mask early"). The issue that this series addresses is the fact that the Nouveau driver invokes the DMA API before setting the DMA mask. In both cases

Hi, Here is my patch queue I accumulated over quite a long time. Patches 1-6 are bugfixes, and rest is mostly RFC. Comments are welcome. Best regards, Maxim Levitsky