search for: nv50_disp_priv

...iff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c index 8b42f45..7ffe2f3 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c @@ -1107,6 +1107,7 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head) u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff; u32 hval, hreg = 0x614200 + (head * 0x800); u32 oval, oreg; + u32 mask; u32 conf = exec_clkcmp(priv, head, 0xff, pclk, &outp); if (conf != ~0) { if (outp.location == 0 && outp.type == DCB_O...

...0x6904c0 0x00000001 0x6904c0 <= 0x1 +[0] 277.973084 MMIO32 R 0x616f98 0x01020038 PDISPLAY+0x6f98 => 0x1020038 +[0] 277.973112 MMIO32 W 0x690480 0x82000000 0x690480 <= 0x82000000 +[0] 277.973139 MMIO32 W 0x616f98 0x41020038 PDISPLAY+0x6f98 <= 0x41020038 +*/ + +int +nve0_hdmi_ctrl(struct nv50_disp_priv *priv, int head, int or, u32 data) +{ + /*if (!(data & NV84_DISP_SOR_HDMI_PWR_STATE_ON)) { + nv_mask(priv, 0x616f98 + hoff, 0x40000000, 0x00000000); + nv_mask(priv, 0x6167a4 + hoff, 0x00000001, 0x00000000); + nv_mask(priv, 0x616714 + hoff, 0x00000001, 0x00000000); + return 0; + }*/ + + /* A...

...7 @@ nv50_disp_base_init(struct nouveau_object *object) } /* ... PIOR caps */ - for (i = 0; i < 3; i++) { + for (i = 0; i < priv->pior.nr; i++) { tmp = nv_rd32(priv, 0x61e000 + (i * 0x800)); nv_wr32(priv, 0x6101f0 + (i * 0x04), tmp); } @@ -834,10 +834,11 @@ exec_script(struct nv50_disp_priv *priv, int head, int id) u8 ver, hdr, cnt, len; u16 data; u32 ctrl = 0x00000000; + u32 reg; int i; /* DAC */ - for (i = 0; !(ctrl & (1 << head)) && i < 3; i++) + for (i = 0; !(ctrl & (1 << head)) && i < priv->dac.nr; i++) ctrl = nv_rd32(p...

...diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdanva3.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdanva3.c index 373dbcc..a19e7d7 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/hdanva3.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/hdanva3.c @@ -36,6 +36,8 @@ nva3_hda_eld(struct nv50_disp_priv *priv, int or, u8 *data, u32 size) if (data && data[0]) { for (i = 0; i < size; i++) nv_wr32(priv, 0x61c440 + soff, (i << 8) | data[i]); + for (; i < 0x60; i++) + nv_wr32(priv, 0x61c440 + soff, (i << 8)); nv_mask(priv, 0x61c448 + soff, 0x80000003, 0x80000003...

...ff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c index f02fd9f..15df527 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c @@ -55,7 +55,14 @@ nv50_dac_sense(struct nv50_disp_priv *priv, int or, u32 loadval) nv_wr32(priv, 0x61a00c + doff, 0x00100000 | loadval); mdelay(9); udelay(500); - nv_wr32(priv, 0x61a00c + doff, 0x80000000); + + /* + * The original nv50 detects a ghost monitor if we do the following + * write. See fdo#67382 for more information + */ + if (nv_de...

These patches are adding support for outputting 2560x1440 at 56 over HDMI. This needs a pixel clock of 225 MHz which was not supported before. This was tested in a dual monitor setup with a GF114 (GTX 560 TI) and one HDMI monitor running with 2560x1440 at 56 and one DVI monitor running with 1920x1200 at 60. This still needs testing on other graphics cards and with dual link DVI. There is no

...-git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c index f065fc2..db8c6fd 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c @@ -55,6 +55,10 @@ nva3_hdmi_ctrl(struct nv50_disp_priv *priv, int head, int or, u32 data) nv_wr32(priv, 0x61c510 + soff, 0x00000000); nv_mask(priv, 0x61c500 + soff, 0x00000001, 0x00000001); + nv_mask(priv, 0x61c5d0 + soff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */ + nv_mask(priv, 0x61c568 + soff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */ + n...

...u/core/engine/disp/dacnv50.c index 61e29d6..98bded6 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c @@ -33,6 +33,12 @@ #include "nv50.h" #include "nouveau_reg.h" +static void +nv50_wait_dpms_ctrl(struct nv50_disp_priv *priv, const u32 dpms_ctrl) +{ + nv_wait(priv, dpms_ctrl, NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING, 0); +} + int nv50_dac_power(NV50_DISP_MTHD_V1) { @@ -56,10 +62,10 @@ nv50_dac_power(NV50_DISP_MTHD_V1) } else return ret; - nv_wait(priv, dpms_ctrl, NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING, 0); + nv...

...gpu/drm/nouveau/core/engine/disp/sornv50.c index 526b752..5238e65 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c @@ -47,8 +47,14 @@ int nv50_sor_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size) { struct nv50_disp_priv *priv = (void *)object->engine; + struct nouveau_bios *bios = nouveau_bios(priv); + const u16 type = (mthd & NV50_DISP_SOR_MTHD_TYPE) >> 12; const u8 head = (mthd & NV50_DISP_SOR_MTHD_HEAD) >> 3; + const u8 link = (mthd & NV50_DISP_SOR_MTHD_LINK) >> 2; const u...

The patches contain some tidy-up work, and refactoring that has arisen as a by-product of my initial work on adding TV support to nv50. Joel Holdsworth (4): drm/nouveau: Removed unneeded include in nvc0_fence.c drm/nouveau: Replaced magic numbers with defines from nouveau_reg drm/nouveau: Replaced copy-pasted nv_wait with nv50_wait_dpms_ctrl helper drm/nouveau: Refactored encoder

...iff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c index 940eaa5..9ad722e 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c @@ -1142,7 +1142,7 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head) if (conf != ~0) { if (outp.location == 0 && outp.type == DCB_OUTPUT_DP) { u32 soff = (ffs(outp.or) - 1) * 0x08; - u32 ctrl = nv_rd32(priv, 0x610798 + soff); + u32 ctrl = nv_rd32(priv, 0x610794 + soff); u32 datarate; switch ((ctrl & 0x000f0000) &gt...

...38e65 100644 >> --- a/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c >> +++ b/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c >> @@ -47,8 +47,14 @@ int >> nv50_sor_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size) >> { >> struct nv50_disp_priv *priv = (void *)object->engine; >> + struct nouveau_bios *bios = nouveau_bios(priv); >> + const u16 type = (mthd & NV50_DISP_SOR_MTHD_TYPE) >> 12; >> const u8 head = (mthd & NV50_DISP_SOR_MTHD_HEAD) >> 3; >> + const u8 link...

...0 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c @@ -695,9 +695,8 @@ nv50_disp_data_ctor(struct nouveau_object *parent, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) { - struct nv50_disp_priv *priv = (void *)engine; struct nouveau_engctx *ectx; - int ret = -EBUSY; + int ret; /* no context needed for channel objects... */ if (nv_mclass(parent) != NV_DEVICE_CLASS) { @@ -707,14 +706,10 @@ nv50_disp_data_ctor(struct nouveau_object *parent, } /* allocate display hardware to cli...

...c > index 526b752..5238e65 100644 > --- a/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c > +++ b/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c > @@ -47,8 +47,14 @@ int > nv50_sor_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size) > { > struct nv50_disp_priv *priv = (void *)object->engine; > + struct nouveau_bios *bios = nouveau_bios(priv); > + const u16 type = (mthd & NV50_DISP_SOR_MTHD_TYPE) >> 12; > const u8 head = (mthd & NV50_DISP_SOR_MTHD_HEAD) >> 3; > + const u8 link = (mthd & NV...