search for: nv50_crc_atomic_set

..._atom *atom); -void nv50_crc_atomic_stop_reporting(struct drm_atomic_state *); -void nv50_crc_atomic_init_notifier_contexts(struct drm_atomic_state *); -void nv50_crc_atomic_release_notifier_contexts(struct drm_atomic_state *); -void nv50_crc_atomic_start_reporting(struct drm_atomic_state *); -void nv50_crc_atomic_set(struct nv50_head *, struct nv50_head_atom *); -void nv50_crc_atomic_clr(struct nv50_head *); +void nv50_crc_atomic_stop_reporting(struct drm_atomic_state *state); +void nv50_crc_atomic_init_notifier_contexts(struct drm_atomic_state *state); +void nv50_crc_atomic_release_notifier_contexts(struct drm...

..._crc_atomic_start_reporting?: ./drivers/gpu/drm/nouveau/dispnv50/crc.h:118:33: error: parameter name omitted 118 | nv50_crc_atomic_start_reporting(struct drm_atomic_state *) {} | ^~~~~~~~~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function ?nv50_crc_atomic_set?: ./drivers/gpu/drm/nouveau/dispnv50/crc.h:120:21: error: parameter name omitted 120 | nv50_crc_atomic_set(struct nv50_head *, struct nv50_head_atom *) {} | ^~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h:120:41: error: parameter name omitted 120 | nv50_crc...

...nv50_crc_atomic_stop_reporting(struct drm_atomic_state *); > -void nv50_crc_atomic_init_notifier_contexts(struct drm_atomic_state *); > -void nv50_crc_atomic_release_notifier_contexts(struct drm_atomic_state *); > -void nv50_crc_atomic_start_reporting(struct drm_atomic_state *); > -void nv50_crc_atomic_set(struct nv50_head *, struct nv50_head_atom *); > -void nv50_crc_atomic_clr(struct nv50_head *); > +void nv50_crc_atomic_stop_reporting(struct drm_atomic_state *state); > +void nv50_crc_atomic_init_notifier_contexts(struct drm_atomic_state > *state); > +void nv50_crc_atomic_release_not...

...break; + } + + if (dcbe->location != DCB_LOC_ON_CHIP) + return NV50_CRC_SOURCE_TYPE_PIOR; + + switch (dcbe->type) { + case DCB_OUTPUT_DP: return NV50_CRC_SOURCE_TYPE_SF; + case DCB_OUTPUT_ANALOG: return NV50_CRC_SOURCE_TYPE_DAC; + default: return NV50_CRC_SOURCE_TYPE_SOR; + } +} + +void nv50_crc_atomic_set(struct nv50_head *head, + struct nv50_head_atom *asyh) +{ + struct drm_crtc *crtc = &head->base.base; + struct drm_device *dev = crtc->dev; + struct nv50_crc *crc = &head->crc; + const struct nv50_crc_func *func = nv50_disp(dev)->core->func->crc; + struct nouveau_encode...

...break; + } + + if (dcbe->location != DCB_LOC_ON_CHIP) + return NV50_CRC_SOURCE_TYPE_PIOR; + + switch (dcbe->type) { + case DCB_OUTPUT_DP: return NV50_CRC_SOURCE_TYPE_SF; + case DCB_OUTPUT_ANALOG: return NV50_CRC_SOURCE_TYPE_DAC; + default: return NV50_CRC_SOURCE_TYPE_SOR; + } +} + +void nv50_crc_atomic_set(struct nv50_head *head, + struct nv50_head_atom *asyh) +{ + struct drm_crtc *crtc = &head->base.base; + struct drm_device *dev = crtc->dev; + struct nv50_crc *crc = &head->crc; + const struct nv50_crc_func *func = nv50_disp(dev)->core->func->crc; + struct nouveau_encode...

...break; + } + + if (dcbe->location != DCB_LOC_ON_CHIP) + return NV50_CRC_SOURCE_TYPE_PIOR; + + switch (dcbe->type) { + case DCB_OUTPUT_DP: return NV50_CRC_SOURCE_TYPE_SF; + case DCB_OUTPUT_ANALOG: return NV50_CRC_SOURCE_TYPE_DAC; + default: return NV50_CRC_SOURCE_TYPE_SOR; + } +} + +void nv50_crc_atomic_set(struct nv50_head *head, + struct nv50_head_atom *asyh) +{ + struct drm_crtc *crtc = &head->base.base; + struct drm_device *dev = crtc->dev; + struct nv50_crc *crc = &head->crc; + const struct nv50_crc_func *func = nv50_disp(dev)->core->func->crc; + struct nouveau_encode...

...break; + } + + if (dcbe->location != DCB_LOC_ON_CHIP) + return NV50_CRC_SOURCE_TYPE_PIOR; + + switch (dcbe->type) { + case DCB_OUTPUT_DP: return NV50_CRC_SOURCE_TYPE_SF; + case DCB_OUTPUT_ANALOG: return NV50_CRC_SOURCE_TYPE_DAC; + default: return NV50_CRC_SOURCE_TYPE_SOR; + } +} + +void nv50_crc_atomic_set(struct nv50_head *head, + struct nv50_head_atom *asyh) +{ + struct drm_crtc *crtc = &head->base.base; + struct drm_device *dev = crtc->dev; + struct nv50_crc *crc = &head->crc; + const struct nv50_crc_func *func = nv50_disp(dev)->core->func->crc; + struct nouveau_encode...

...); -void nv50_crc_atomic_prepare_notifier_contexts(struct drm_atomic_state *); +void nv50_crc_atomic_init_notifier_contexts(struct drm_atomic_state *); +void nv50_crc_atomic_release_notifier_contexts(struct drm_atomic_state *); void nv50_crc_atomic_start_reporting(struct drm_atomic_state *); void nv50_crc_atomic_set(struct nv50_head *, struct nv50_head_atom *); void nv50_crc_atomic_clr(struct nv50_head *); @@ -108,12 +111,15 @@ static inline void nv50_crc_handle_vblank(struct nv50_head *head) { return 0; } static inline int -nv50_crc_atomic_check(struct nv50_head *, struct nv50_head_atom *, - struc...

Nvidia released some documentation on how CRC support works on their GPUs, hooray! So: this patch series implements said CRC support in nouveau, along with adding some special debugfs interfaces for some relevant igt-gpu-tools tests that we'll be sending in just a short bit. This additionally adds a feature that Ville Syrj?l? came up with: vblank works. Basically, this is just a generic DRM

Nvidia released some documentation on how CRC support works on their GPUs, hooray! So: this patch series implements said CRC support in nouveau, along with adding some special debugfs interfaces for some relevant igt-gpu-tools tests (already on the ML). First - we add some new functionality to kthread_work in the kernel, and then use this to add a new feature to DRM that Ville Syrj?l? came up

Nvidia released some documentation on how CRC support works on their GPUs, hooray! So: this patch series implements said CRC support in nouveau, along with adding some special debugfs interfaces for some relevant igt-gpu-tools tests that we'll be sending in just a short bit. This additionally adds a feature that Ville Syrj?l? came up with: vblank works. Basically, this is just a generic DRM

Nvidia released some documentation on how CRC support works on their GPUs, hooray! So: this patch series implements said CRC support in nouveau, along with adding some special debugfs interfaces for some relevant igt-gpu-tools tests (already on the ML). First - we add some new functionality to kthread_work in the kernel, and then use this to add a new feature to DRM that Ville Syrj?l? came up

Nvidia released some documentation on how CRC support works on their GPUs, hooray! So: this patch series implements said CRC support in nouveau, along with adding some special debugfs interfaces for some relevant igt-gpu-tools tests (already on the ML). First - we add some new functionality to kthread_work in the kernel, and then use this to add a new feature to DRM that Ville Syrj?l? came up

Nvidia released some documentation on how CRC support works on their GPUs, hooray! So: this patch series implements said CRC support in nouveau, along with adding some special debugfs interfaces for some relevant igt-gpu-tools tests (already on the ML). First - we add some new functionality to kthread_work in the kernel, and then use this to add a new feature to DRM that Ville Syrj?l? came up

Hello, while I debugged an issue in the imx-lcdc driver I was constantly irritated about struct drm_device pointer variables being named "dev" because with that name I usually expect a struct device pointer. I think there is a big benefit when these are all renamed to "drm_dev". I have no strong preference here though, so "drmdev" or "drm" are fine for me,

Hello, while I debugged an issue in the imx-lcdc driver I was constantly irritated about struct drm_device pointer variables being named "dev" because with that name I usually expect a struct device pointer. I think there is a big benefit when these are all renamed to "drm_dev". I have no strong preference here though, so "drmdev" or "drm" are fine for me,