Displaying 7 results from an estimated 7 matches for "nv50_clear_depth_stencil".
2014 May 21
2
[Mesa-dev] [PATCH 02/12] nv50: setup scissors on clear_render_target/depth_stencil
...arget(struct pipe_context *pipe,
> (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
> }
>
> - nv50->dirty |= NV50_NEW_FRAMEBUFFER;
> + nv50->dirty |= NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR;
> }
>
> static void
> @@ -364,6 +372,14 @@ nv50_clear_depth_stencil(struct pipe_context *pipe,
>
> PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
>
> + BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
> + PUSH_DATA (push, ( width << 16) | dstx);
> + PUSH_DATA (push, (height << 16) | dsty);
> + BEGIN_NV04...
2014 Feb 13
2
[PATCH] nv50: make sure to clear _all_ layers of all attachments
...ush, NV50_3D_RT_HORIZ_LINEAR | mt->level[0].pitch);
PUSH_DATA (push, sf->height);
BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
- PUSH_DATA (push, 1);
+ PUSH_DATA (push, 512);
if (!nouveau_bo_memtype(bo)) {
BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
@@ -366,7 +366,7 @@ nv50_clear_depth_stencil(struct pipe_context *pipe,
PUSH_DATA (push, bo->offset + sf->offset);
PUSH_DATA (push, nv50_format_table[dst->format].rt);
PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
- PUSH_DATA (push, 0);
+ PUSH_DATA (push, mt->layer_stride >> 2);
BEGIN...
2014 May 20
0
[PATCH 02/12] nv50: setup scissors on clear_render_target/depth_stencil
..., 5);
@@ -325,7 +333,7 @@ nv50_clear_render_target(struct pipe_context *pipe,
(z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
}
- nv50->dirty |= NV50_NEW_FRAMEBUFFER;
+ nv50->dirty |= NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR;
}
static void
@@ -364,6 +372,14 @@ nv50_clear_depth_stencil(struct pipe_context *pipe,
PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
+ BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
+ PUSH_DATA (push, ( width << 16) | dstx);
+ PUSH_DATA (push, (height << 16) | dsty);
+ BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2...
2014 May 21
0
[Mesa-dev] [PATCH 02/12] nv50: setup scissors on clear_render_target/depth_stencil
...>> (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
>> }
>>
>> - nv50->dirty |= NV50_NEW_FRAMEBUFFER;
>> + nv50->dirty |= NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR;
>> }
>>
>> static void
>> @@ -364,6 +372,14 @@ nv50_clear_depth_stencil(struct pipe_context *pipe,
>>
>> PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
>>
>> + BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
>> + PUSH_DATA (push, ( width << 16) | dstx);
>> + PUSH_DATA (push, (height << 16) | dsty);...
2014 May 20
14
[PATCH 00/12] Cherry-pick nv50/nvc0 patches from gallium-nine
I went through the gallium-nine tree and picked out nouveau patches that are
general bug-fixes. The first bunch I'd like to also get into 10.2. I've
reviewed all of them and they make sense to me, but sending them out for
public review as well in case there are any objections.
Unless I hear objections, I'd like to push this by Friday.
Christoph Bumiller (11):
nv50,nvc0: always pull
2014 Sep 01
2
[PATCH 1/3] nv50: set the miptree address when clearing bo's in vp2 init
The mt address is about to be used more, make sure it's set
appropriately.
Reported-by: Emil Velikov <emil.l.velikov at gmail.com>
Tested-by: Emil Velikov <emil.l.velikov at gmail.com>
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable at lists.freedesktop.org>
---
src/gallium/drivers/nouveau/nv50/nv84_video.c | 2 ++
1 file
2016 Jun 05
0
[RFC PATCH] nouveau: add locking
..._clear_render_target(struct pipe_context *pipe,
BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
PUSH_DATA (push, nv50->cond_condmode);
+ pipe_mutex_unlock(nv50->screen->base.push_mutex);
+
nv50->dirty_3d |= NV50_NEW_3D_FRAMEBUFFER | NV50_NEW_3D_SCISSOR;
}
@@ -376,6 +387,8 @@ nv50_clear_depth_stencil(struct pipe_context *pipe,
assert(dst->texture->target != PIPE_BUFFER);
assert(nouveau_bo_memtype(bo)); /* ZETA cannot be linear */
+ pipe_mutex_lock(nv50->screen->base.push_mutex);
+
if (clear_flags & PIPE_CLEAR_DEPTH) {
BEGIN_NV04(push, NV50_3D(CLEAR_DEPTH),...