search for: nv124_chipset

...ice/base.c +++ b/drm/nouveau/nvkm/engine/device/base.c @@ -2043,6 +2043,7 @@ nv120_chipset = { .mxm = nv50_mxm_new, .pci = gk104_pci_new, .pmu = gm107_pmu_new, + .therm = gm200_therm_new, .secboot = gm200_secboot_new, .timer = gk20a_timer_new, .top = gk104_top_new, @@ -2077,6 +2078,7 @@ nv124_chipset = { .mxm = nv50_mxm_new, .pci = gk104_pci_new, .pmu = gm107_pmu_new, + .therm = gm200_therm_new, .secboot = gm200_secboot_new, .timer = gk20a_timer_new, .top = gk104_top_new, @@ -2111,6 +2113,7 @@ nv126_chipset = { .mxm = nv50_mxm_new, .pci = gk104_pci_new, .pmu = gm107_pmu_new, +...

...em_new, .ltc = gm107_ltc_new, .mc = gk20a_mc_new, @@ -1974,6 +1991,7 @@ nv120_chipset = { .gpio = gk104_gpio_new, .i2c = gm200_i2c_new, .ibus = gm200_ibus_new, + .iccsense = gf100_iccsense_new, .imem = nv50_instmem_new, .ltc = gm200_ltc_new, .mc = gk20a_mc_new, @@ -2004,6 +2022,7 @@ nv124_chipset = { .gpio = gk104_gpio_new, .i2c = gm200_i2c_new, .ibus = gm200_ibus_new, + .iccsense = gf100_iccsense_new, .imem = nv50_instmem_new, .ltc = gm200_ltc_new, .mc = gk20a_mc_new, @@ -2035,6 +2054,7 @@ nv126_chipset = { .gpio = gk104_gpio_new, .i2c = gm200_i2c_new, .ibus = gm200_ibus_...

...em_new, .ltc = gk104_ltc_new, .mc = gk20a_mc_new, @@ -1943,6 +1959,7 @@ nv117_chipset = { .gpio = gk104_gpio_new, .i2c = gf119_i2c_new, .ibus = gk104_ibus_new, + .iccsense = gf100_iccsense_new, .imem = nv50_instmem_new, .ltc = gm107_ltc_new, .mc = gk20a_mc_new, @@ -1974,6 +1991,7 @@ nv124_chipset = { .gpio = gk104_gpio_new, .i2c = gm204_i2c_new, .ibus = gm204_ibus_new, + .iccsense = gf100_iccsense_new, .imem = nv50_instmem_new, .ltc = gm204_ltc_new, .mc = gk20a_mc_new, @@ -2005,6 +2023,7 @@ nv126_chipset = { .gpio = gk104_gpio_new, .i2c = gm204_i2c_new, .ibus = gm204_ibus_...

overall it is for the most part the same as my older version. I cleaned up some copyright things, so that it is more like the others. Also I moved the print about the max speed supported into preinit and did some other minor cleanups in the 3rd commit. Happy testing (and performance for prime offloading setups) Karol Herbst (9): pci: add gk104 variant pci: add gf106 variant pci: implement

The INA3221 is usually found on mid and high end kepler+ gpus Marins Patch implements the new iccsense subdev and all needed bits for the INA3221 power sensor. My Patch implements the hwmon power1 interface to expose the current power consumption through hwmon (and can be read out via sysfs or the sensors tool) Please test these patches for Fermi+ GPUs, that nothing gets messed up and works as

This is a complete rework from the first version I sent out. Now the implementation is more centered around the power_rails we find in the SENSE table instead of extdev centered. This makes the implementation a lot easier and straightforward. I've added support for the INA219, INA209 and INA3221 sensors found on multiple Fermi and Kepler cards. The power consumption is also exported via

This is a complete rework from the last version I sent out. Now the implementation is more centered around the power_rails we find in the SENSE table instead of extdev centered. This makes the implementation a lot easier and straightforward. I've added support for the INA219, INA209 and INA3221 sensors found on multiple Fermi and Kepler cards, but only the INA3221 bits are tested so far.

This is a complete rework from the first version I sent out. Now the implementation is more centered around the power_rails we find in the SENSE table instead of extdev centered. This makes the implementation a lot easier and straightforward. I've added support for the INA219, INA209 and INA3221 sensors found on multiple Fermi and Kepler cards. The power consumption is also exported via

...uct nvkm_device *, int, struct nvkm_secboot **); + #endif diff --git a/drm/nouveau/nvkm/engine/device/base.c b/drm/nouveau/nvkm/engine/device/base.c index ba44ba925f4b..ab56abac0bc5 100644 --- a/drm/nouveau/nvkm/engine/device/base.c +++ b/drm/nouveau/nvkm/engine/device/base.c @@ -2022,6 +2022,7 @@ nv124_chipset = { .fifo = gm200_fifo_new, .gr = gm200_gr_new, .sw = gf100_sw_new, + .secboot = gm200_secboot_new, }; static const struct nvkm_device_chip @@ -2053,6 +2054,7 @@ nv126_chipset = { .fifo = gm200_fifo_new, .gr = gm206_gr_new, .sw = gf100_sw_new, + .secboot = gm200_secboot_new, };...

this patch series implements PCIe speed changes for Tesla and newer. The Kepler and Fermi bits are tested on my cards at home. Karol Herbst (9): pci: add gk104 variant pci: add gf106 variant pci: implement generic code for PCIe speed change pci: implement pcie speed change for tesla pci: implement pcie speed change on Fermi pci: implement PCIe speed change for kepler+ bios/perf:

This is a complete rework from the first version I sent out. Now the implementation is more centered around the power_rails we find in the SENSE table instead of extdev centered. This makes the implementation a lot easier and straightforward. I've added support for the INA219, INA209 and INA3221 sensors found on multiple Fermi and Kepler cards. The power consumption is also exported via

overall the same as the old stuff, but with better namings and tirivialy improved code here and there Karol Herbst (9): pci: add gk104 variant pci: add gf106 variant pci: implement generic code for PCIe speed change pci: implement pcie speed change for tesla pci: implement pcie speed change on Fermi pci: implement PCIe speed change for kepler+ bios/perf: parse the pci speed from the

This is a highly changed revision of the first patch series that adds secure boot support to Nouveau. This code still depends on NVIDIA releasing official firmware files, but the files released with SHIELD TV and Pixel C can already be used on a Jetson TX1. As you know we are working hard to release the official firmware files, however in the meantime it doesn't hurt to review the code so it

New version of the secure boot code that works with the blobs just merged into linux-firmware. Since the required Mesa patches are also merged, this set is the last piece of the puzzle to get out-of-the-box accelerated Maxwell 2. The basic code remains the same, with a few improvements with respect to how secure falcons are started. Hopefully the patchset is better split too. I have a

Last update here: https://lists.freedesktop.org/archives/nouveau/2017-September/028848.html Basically big cleanup, reordering, simplifications and some renaming to make the code easier to read and to review. I also moved some bugfixes to the front so they can be merged prior the other patches. There was also a bug related to the therm daemon triggering a pstate change leading to PMU lockups,

Just wanted to post updated versions of my last series/patches. Reviews welcomed. It would be also nice if we agree on features I should focus upstreaming, so that this work can be better splitted or reordered. Sadly most of my patches depend on the rather big clk subdev rework and I think those patches shows best, why I think this rework is actually needed and makes things much easier to add