Displaying 2 results from an estimated 2 matches for "nv11_subchan_dma_semaphore".
2012 Dec 20
0
reproducible CACHE_ERRORS
...ually the error looks like this (with a bit improved logging):
nouveau E[ PFIFO][0000:02:00.0] CACHE_ERROR - ch 6 [glxgears[15559]] subc 0 mthd 0x0060 data 0x8000000f c1p0 0x20000010 HASH_FAILED (unknown bits 0x20000000) c1_hash 0x00000436
What I found so far:
1) It's triggered by setting of NV11_SUBCHAN_DMA_SEMAPHORE to NvSema
(0x8000000f) in nv84_fence_emit. Hw tells us it cannot find ramht entry
for NvSema object (NV04_PFIFO_CACHE1_PULL0 == HASH_FAILED, frequently
unknown 30th bit is set)
2) In 95% cases CACHE_ERRORs are triggered on glxgears channel.
3) RAMHT entry was definitely created and used ma...
2013 Nov 12
6
[PATCH 1/7] drm/nouveau: fix m2mf copy to tiled gart
From: Maarten Lankhorst <maarten.lankhorst at canonical.com>
Commit de7b7d59d54852c introduced tiled GART, but a linear copy is
still performed. This may result in errors on eviction, fix it by
checking tiling from memtype.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst at canonical.com>
Cc: stable at vger.kernel.org #3.10+
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drivers/gpu/drm/nouveau/nouveau_bo.c | 33