Displaying 2 results from an estimated 2 matches for "nv10_pgraph_ctx_control".
2009 Nov 06
2
[PATCH 1/2] drm/nv10: Keep the lower bits of PGRAPH_CTX_USER during context switches.
...ouveau/nv10_graph.c b/drivers/gpu/drm/nouveau/nv10_graph.c
index cf5c9c4..6bf6804 100644
--- a/drivers/gpu/drm/nouveau/nv10_graph.c
+++ b/drivers/gpu/drm/nouveau/nv10_graph.c
@@ -673,7 +673,8 @@ int nv10_graph_load_context(struct nouveau_channel *chan)
nv10_graph_load_pipe(chan);
nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
- nv_wr32(dev, NV10_PGRAPH_CTX_USER, chan->id << 24);
+ tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER);
+ nv_wr32(dev, NV10_PGRAPH_CTX_USER, (tmp & 0xffffff) | chan->id << 24);
tmp = nv_rd32(dev, NV10_PGRAPH_FFINTFC_ST2);
nv_wr32(dev, NV10_PGRAPH_FFINTFC_ST2, tmp &...
2009 Dec 11
5
[PATCH 1/3] drm/nouveau: Pre-G80 tiling support.
...V40_PGRAPH_TSIZE0(i) ?? */
- nv_wr32(dev, 0x00400900 + i * 0x10,
- nv_rd32(dev, NV10_PFB_TILE(i)));
- /* which is NV40_PGRAPH_TILE0(i) ?? */
- }
+ /* Turn all the tiling regions off. */
+ for (i = 0; i < NV10_PFB_TILE__SIZE; i++)
+ nv20_graph_write_tile(dev, i, 0, 0, 0);
nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF);
diff --git a/drivers/gpu/drm/nouveau/nv40_fb.c b/drivers/gpu/drm/nouveau/nv40_fb.c
index ca1d271..3cd07d8 100644
--- a/drivers/gpu/drm/nouveau/nv40_fb.c
+++ b/drivers/gpu/drm/nouveau/nv40_fb.c
@@ -3,12 +3,37 @@
#include "nouve...