Displaying 6 results from an estimated 6 matches for "nv04_pll_calc".
2017 Jan 10
0
[bug report] drm/nouveau/devinit: move simple pll setting routines to devinit
...2 int ret;
43
44 ret = nvbios_pll_parse(bios, type, &info);
45 if (ret) {
46 nvkm_error(subdev, "failed to retrieve pll data, %d\n", ret);
47 return ret;
48 }
49
50 ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P);
51 if (!ret) {
52 nvkm_error(subdev, "failed pll calculation\n");
53 return ret;
This should probably be a negative error code instead of "ret"?
54...
2015 Oct 12
2
fixing GDDR5 reclocking on kepler cards
this is my first patch on the list through git send-mail and I hope everything
is set up right, sorry for the noise here, but I don't want to try with an
empty mail :)
as the subject already says, this patch fixes one of the more serious issues
while reclocking gddr5 on kepler cards. It works for me and for a bunch of others
I met on IRC.
Karol Herbst (1):
pll/gk104: fix PLL instability
2017 Jul 29
0
[PATCH] nouveau: Fix declarations with incorrect variables.
..._new(struct nvkm_dma *, const struct nvkm_oclass *, void *, u32,
diff --git a/drm/nouveau/nvkm/subdev/clk/pll.h b/drm/nouveau/nvkm/subdev/clk/pll.h
index 44020a30..adcf287f 100644
--- a/drm/nouveau/nvkm/subdev/clk/pll.h
+++ b/drm/nouveau/nvkm/subdev/clk/pll.h
@@ -7,5 +7,5 @@ struct nvbios_pll;
int nv04_pll_calc(struct nvkm_subdev *, struct nvbios_pll *, u32 freq,
int *N1, int *M1, int *N2, int *M2, int *P);
int gt215_pll_calc(struct nvkm_subdev *, struct nvbios_pll *, u32 freq,
- int *N, int *fN, int *M, int *P);
+ int *pN, int *pfN, int *pM, int *P);
#endif
diff --git a/drm/nouveau/nvkm/subd...
2013 Nov 16
0
[PATCH] drm/nouveau/clk: Implement reclocking for NVAA/NVAC
...nouveau_bios(priv);
+ struct nvbios_pll pll;
+ struct nouveau_clock *clk = &priv->base;
+ int ret;
+
+ ret = nvbios_pll_parse(bios, reg, &pll);
+ if (ret)
+ return 0;
+
+ pll.vco2.max_freq = 0;
+ pll.refclk = clk->read(clk, nv_clk_src_href);
+ if (!pll.refclk)
+ return 0;
+
+ return nv04_pll_calc(nv_subdev(priv), &pll, clock, N, M, NULL, NULL, P);
+}
+
+static inline u32
+calc_P(u32 src, u32 target, int *div)
+{
+ u32 clk0 = src, clk1 = src;
+ for (*div = 0; *div <= 7; (*div)++) {
+ if (clk0 <= target) {
+ clk1 = clk0 << (*div ? 1 : 0);
+ break;
+ }
+ clk0 >>= 1...
2013 Nov 17
0
[PATCH] drm/nouveau/clk: Implement reclocking for NVAA/NVAC
...nouveau_bios(priv);
+ struct nvbios_pll pll;
+ struct nouveau_clock *clk = &priv->base;
+ int ret;
+
+ ret = nvbios_pll_parse(bios, reg, &pll);
+ if (ret)
+ return 0;
+
+ pll.vco2.max_freq = 0;
+ pll.refclk = clk->read(clk, nv_clk_src_href);
+ if (!pll.refclk)
+ return 0;
+
+ return nv04_pll_calc(nv_subdev(priv), &pll, clock, N, M, NULL, NULL, P);
+}
+
+static inline u32
+calc_P(u32 src, u32 target, int *div)
+{
+ u32 clk0 = src, clk1 = src;
+ for (*div = 0; *div <= 7; (*div)++) {
+ if (clk0 <= target) {
+ clk1 = clk0 << (*div ? 1 : 0);
+ break;
+ }
+ clk0 >>= 1...
2013 Nov 09
2
[PATCH] drm/nouveau/clk: Initial implementation for reclocking NVAA/NVAC
Reclocking of NVAA/NVAC is substantially different from NV50+, enough to justify a separate clock implementation. This code is a forward-port of reclocking code that has been sitting in a branch for a while, and has been tested on my NVAC. Traces show no significant reasons why this shouldn't work on NVAA, but testers are always welcome. And since these are IGPs without dedicated RAM to