Displaying 2 results from an estimated 2 matches for "nv04_fifo_priv".
2012 Dec 05
2
[RFC PATCH] drm/nouveau: report channel owner in error messages
...nclude <core/os.h>
#include <core/class.h>
+#include <core/client.h>
#include <core/engctx.h>
#include <core/namedb.h>
#include <core/handle.h>
@@ -398,10 +399,29 @@ out:
return handled;
}
+static struct nouveau_client *
+nv04_fifo_client_for_chid(struct nv04_fifo_priv *priv, u32 chid)
+{
+ struct nouveau_fifo_chan *chan;
+ struct nouveau_client *client = NULL;
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->base.lock, flags);
+ if (chid >= priv->base.min &&
+ chid <= priv->base.max) {
+ chan = (void *)priv->base.channel[chid]...
2012 Dec 09
0
[PATCH 1/4] drm/nouveau: split fifo interrupt handler
...rm/nouveau/core/engine/fifo/nv04.c
index 2fe14da3..76944c4 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
@@ -398,6 +398,92 @@ out:
return handled;
}
+static void
+nv04_fifo_cache_error(struct nouveau_device *device,
+ struct nv04_fifo_priv *priv, u32 chid, u32 get)
+{
+ u32 mthd, data;
+ int ptr;
+
+ /* NV_PFIFO_CACHE1_GET actually goes to 0xffc before wrapping on my
+ * G80 chips, but CACHE1 isn't big enough for this much data.. Tests
+ * show that it wraps around to the start at GET=0x800.. No clue as to
+ * why..
+ */
+ pt...