search for: nv04_clock_pll_calc

...644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c @@ -90,6 +90,7 @@ nv50_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return ret; priv->base.pll_set = nv50_clock_pll_set; + priv->base.pll_calc = nv04_clock_pll_calc; return 0; } -- 1.7.12

...com> --- diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h index 39e73b9..41b7a6a 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h +++ b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h @@ -54,6 +54,7 @@ int nv04_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *, int clk, struct nouveau_pll_vals *); int nv04_clock_pll_prog(struct nouveau_clock *, u32 reg1, struct nouveau_pll_vals *); - +int nva3_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *, + int clk, struct nouveau_pll_vals *); #endif...

..._oclass nva3_clock_oclass; >> extern struct nouveau_oclass nvc0_clock_oclass; >> extern struct nouveau_oclass nve0_clock_oclass; >> +extern struct nouveau_oclass gk20a_clock_oclass; >> int nv04_clock_pll_set(struct nouveau_clock *, u32 type, u32 freq); >> int nv04_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *, >> diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c >> b/drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c >> new file mode 100644 >> index 000000000000..e175cfda0a48 >> --- /dev/null >> +++ b/drivers/gpu...

...struct nouveau_oclass nva3_clock_oclass; > extern struct nouveau_oclass nvc0_clock_oclass; > extern struct nouveau_oclass nve0_clock_oclass; > +extern struct nouveau_oclass gk20a_clock_oclass; > > int nv04_clock_pll_set(struct nouveau_clock *, u32 type, u32 freq); > int nv04_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *, > diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c b/drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c > new file mode 100644 > index 000000000000..e175cfda0a48 > --- /dev/null > +++ b/drivers/gpu/drm/nouveau/core/subdev/cloc...

...oclass *nvaa_clock_oclass; extern struct nouveau_oclass nva3_clock_oclass; extern struct nouveau_oclass nvc0_clock_oclass; extern struct nouveau_oclass nve0_clock_oclass; +extern struct nouveau_oclass gk20a_clock_oclass; int nv04_clock_pll_set(struct nouveau_clock *, u32 type, u32 freq); int nv04_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *, diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c b/drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c new file mode 100644 index 000000000000..e175cfda0a48 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c @@ -0,0 +1,670...

This series adds support for reclocking on GK20A. The first two patches touch the clock subsystem to allow GK20A to operate, by making the presence of the thermal and voltage devices optional, and allowing pstates to be provided directly instead of being probed using the BIOS (which Tegra does not have). The last patch adds the GK20A clock device. Arguably the clock can be seen as a stripped-down

Second version of the gk20a clock patches. I have tried to keep the therm and volt devices mandatory in the clock driver, but unfortunately they are too tied to bios to allow this, at least for the moment. Consequently this version is mostly a port of the first version to Ben's tree. Ben, please let me know what I have done wrong in terms of integration to your tree, as the main purpose of