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Hello. I am trying to vectorize a CSR SpMV (sparse matrix vector multiplication) procedure but the LLVM loop vectorizer is not able to handle such code. I am using cland and llvm version 3.4 (on Ubuntu 12.10). I use the -fvectorize option with clang and -loop-vectorize with opt-3.4 . The CSR SpMV function is inspired from

...pple.com Cc: llvm-dev at lists.llvm.org; Demikhovsky, Elena <elena.demikhovsky at intel.com>; Amara Emerson <amara.emerson at arm.com>; Stotzer, Eric <estotzer at ti.com>; Nemanja Ivanovic <nemanja.i.ibm at gmail.com>; Kreitzer, David L <david.l.kreitzer at intel.com>; Nuzman, Dorit <dorit.nuzman at intel.com>; Adam Nemet <anemet at apple.com>; James Molloy <James.Molloy at arm.com>; Sander De Smalen <Sander.DeSmalen at arm.com>; Zaks, Ayal <ayal.zaks at intel.com>; Graham Hunter <Graham.Hunter at arm.com>; Michael Kuperstein <mkup...

...her scalar values to vector, >>> which might be slow (and thus, vectorizer might decide to leave the code scalar). >>> >>> And here is a list of papers vectorizer is based on: >>> // The reduction-variable vectorization is based on the paper: >>> // D. Nuzman and R. Henderson. Multi-platform Auto-vectorization. >>> // >>> // Variable uniformity checks are inspired by: >>> // Karrenberg, R. and Hack, S. Whole Function Vectorization. >>> // >>> // The interleaved access vectorization is based on the paper: &gt...

...; Hal Finkel <hfinkel at anl.gov>; Demikhovsky, Elena <elena.demikhovsky at intel.com>; Amara Emerson <amara.emerson at arm.com>; Stotzer, Eric <estotzer at ti.com>; Nemanja Ivanovic <nemanja.i.ibm at gmail.com>; Kreitzer, David L <david.l.kreitzer at intel.com>; Nuzman, Dorit <dorit.nuzman at intel.com>; Adam Nemet <anemet at apple.com>; James Molloy <James.Molloy at arm.com>; Sander De Smalen <Sander.DeSmalen at arm.com>; Zaks, Ayal <ayal.zaks at intel.com>; Graham Hunter <Graham.Hunter at arm.com>; Michael Kuperstein <mkup...

...; Hal Finkel <hfinkel at anl.gov>; Demikhovsky, Elena <elena.demikhovsky at intel.com>; Amara Emerson <amara.emerson at arm.com>; Stotzer, Eric <estotzer at ti.com>; Nemanja Ivanovic <nemanja.i.ibm at gmail.com>; Kreitzer, David L <david.l.kreitzer at intel.com>; Nuzman, Dorit <dorit.nuzman at intel.com>; Adam Nemet <anemet at apple.com>; James Molloy <James.Molloy at arm.com>; Sander De Smalen <Sander.DeSmalen at arm.com>; Zaks, Ayal <ayal.zaks at intel.com>; Graham Hunter <Graham.Hunter at arm.com>; Michael Kuperstein <mkup...

...o vector, which might be slow >>>>> (and thus, vectorizer might decide to leave the code scalar). >>>>> >>>>> And here is a list of papers vectorizer is based on: // The reduction-variable >>>>> vectorization is based on the paper: // D. Nuzman and R. Henderson. >>>>> Multi-platform Auto-vectorization. // // Variable uniformity checks are inspired >>>>> by: // Karrenberg, R. and Hack, S. Whole Function Vectorization. // // The >>>>> interleaved access vectorization is based on the paper: // D...

...o vector, which might be slow >>>>> (and thus, vectorizer might decide to leave the code scalar). >>>>> >>>>> And here is a list of papers vectorizer is based on: // The reduction-variable >>>>> vectorization is based on the paper: // D. Nuzman and R. Henderson. >>>>> Multi-platform Auto-vectorization. // // Variable uniformity checks are inspired >>>>> by: // Karrenberg, R. and Hack, S. Whole Function Vectorization. // // The >>>>> interleaved access vectorization is based on the paper: // D...

...simply can't perform misaligned accesses, and for wide vector processors with many lanes this problem is equally important and even more complex. People have already addressed in a platform-independent way realignment of misaligned vector memory accesses - see, for example for GCC a paper of Nuzman and Henderson ("Multi-platform Auto-vectorization", CGO 2006, https://www.researchgate.net/publication/4231612_Multi-platform_auto-vectorization). It would be interesting to address this issue of realignment of misaligned vector memory accesses in LLVM - this seems to be already we...

> On 5 Jan 2018, at 21:01, Saito, Hideki via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > All, > > I'm trying to refactor LoopVectorize such that it has better conformance to VPlan vision going forward > (http://www.llvm.org/docs/Proposals/VectorizationPlan.html). All VP*Recipe class definitions are now > moved to VPlan.h, and I have a patch under review

...r Committee Members: Christoph Dubach, University of Edinburgh Benoit Dupont de Dinechin, Kalray Kemal Ebcioglu, Global Supercomputing Lieven Eeckhout, University of Ghent R. Govindarajan, Indian Institute of Science Boris Grot, University of Edinburgh Christoph Kessler, Linkoping University Dorit Nuzman, Intel Rodric Rabbah, IBM Ronny Ronen, Intel Xipeng Shen, North Carolina State University Gabriel M. Silberman, Dell Research Zehra Sura, IBM CONTACT For questions regarding the submission process, or for additional information, clarifications, or questions, please contact the ACM Student Research...

All, I'm trying to refactor LoopVectorize such that it has better conformance to VPlan vision going forward (http://www.llvm.org/docs/Proposals/VectorizationPlan.html). All VP*Recipe class definitions are now moved to VPlan.h, and I have a patch under review to move LoopVectorizationPlanner class out of LoopVectorize.cpp (https://reviews.llvm.org/D41420). Next thing I'm working on is

Hello, I am applying for Google Summer of Code with a project related to LLVM and Connex SIMD processor and I would appreciate some feedback on the proposal. The proposal can be found here: https://docs.google.com/document/d/1pBRbW8pU9GV8zWCJQrILhynNEBpGXJKtev1j7ekXfqs/edit?usp=sharing Thank you, Andrei Popa

...ave the innermost Loop Vectorizer explicitly model the control flow of its vectorized loop. More will be presented in our technical talk at the upcoming LLVM Developers' Meeting. References: ----------- [1] "Outer-loop vectorization: revisited for short SIMD architectures", Dorit Nuzman and Ayal Zaks, PACT 2008. [2] "Proposal for function vectorization and loop vectorization with function calls", Xinmin Tian, [cfe-dev] March 2, 2016 (http://lists.llvm.org/pipermail/cfe-dev/2016-March/047732.html. See also https://reviews.llvm.org/D22792). [3] "Throttling Automatic...

...y allows us to handle simple cases. Also, as a follow-up, we want to build on the infrastructure described in this RFC to enable vectorization using new HW instructions that operate on compund values, like FCADD and FCMLA in Armv8.3-a. [1] "Loop-Aware SLP in GCC" by Ira Rosen, Dorit Nuzman, Ayal Zaks. Thanks for bearing with me! I am looking forward to any thoughts & feedback! Cheers, Florian

...only allows us to handle simple cases. Also, as a follow-up, we want to build on the infrastructure described in this RFC to enable vectorization using new HW instructions that operate on compund values, like FCADD and FCMLA in Armv8.3-a. [1] "Loop-Aware SLP in GCC" by Ira Rosen, Dorit Nuzman, Ayal Zaks. Thanks for bearing with me! I am looking forward to any thoughts & feedback! Cheers, Florian _______________________________________________ LLVM Developers mailing list llvm-dev at lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev