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...rking on the backend for an architecture which has a compare instruction that affects only an internal condition code register (basically a sub without destination register). I get the following assert in the scheduling phase: llvm::SDNode::getValueType(unsigned int) const: Assertion `ResNo < NumValues && "Illegal result number!"' failed. It turns out that ResNo and NumValues are both 1, which makes me think somehow the no-result aspect has not been properly modelized. Therefore, I suspect my tablegen description of this instruction to be erroneous, so I paste it below wi...

.... One way to handle this might be to expand the use of SubclassData. There are 15 bits to play with and only the bottom 6-7 are in use (if I am reading it right). We can also reduce the width of following field NodeId (do we need 32-bit for it?) and widen SubclassData. Also, NumOperands and NumValues can be changed to take up fewer bits. I don't think we need 16-bits for each. So NodeType, OperandsNeedDelete, SubclassData, NodeId, NumOperands, and NumValues together are using 96 bits (assuming int is 32-bit and short is 16-bit). I think there is opportunity here to re-pack them a...

...ally a sub without destination register). You want to model the condition codes as a pseudo-register rather than using OutFlag. See the X86 back end. > I get the following assert in the scheduling phase: > > llvm::SDNode::getValueType(unsigned int) const: Assertion `ResNo < > NumValues && "Illegal result number!"' failed. > > It turns out that ResNo and NumValues are both 1, which makes me > think somehow the no-result aspect has not been properly modelized. > Therefore, I suspect my tablegen description of this instruction to > be err...

...f following > field NodeId (do we need 32-bit for it?) and widen SubclassData. Yep. See my response to Dan. I don't know how many target-specific flags you need, but we should be able to carve out four more bits from SubclassData without changing anything else. > Also, NumOperands and NumValues can be changed to take up fewer bits. > I don't think we need 16-bits for each. Probably true. > So NodeType, OperandsNeedDelete, SubclassData, NodeId, NumOperands, > and NumValues together are using 96 bits (assuming int is 32-bit and > short is 16-bit). I think there is opport...

Dear All, I currently have one of my transforms creating the following store instruction: store [65536 x i8] zeroinitializer, [65536 x i8]* %buf.i, align 16 ... which causes the SelectionDAG code to assert out: Assertion failed: (ResNo < NumValues && "Illegal result number!"), function getValueType, file /Users/criswell/src/llvm/include/llvm/CodeGen/SelectionDAGNodes.h, line 589. Should LLVM be able to code generate the above store instruction? If not, how large a value can a store instruction store to memory without...

Right now the MemSDNode keeps a volatile bit in the SubclassData to mark volatile memory operations. We have some changes we'd like to push back that adds a NonTemporal flag to MemSDNode to mark instructions where movnt (on x86) and other goodness can happen (we'll also add the TableGen patterns to properly select movnt). In our tree we simply added another flag to the MemSDNode

.... My intrinsic is defined as: Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],[IntrReadWriteArgMem]>; i.e. it has four arguments and one return value In DAGToDAGISel when I try to pass it with four arguments and a return register it fails the assertion `ResNo < NumValues && "Illegal result number!"'. More specifically I am doing something like: EVT ReturnValueVT = Node->getValueType(0) ; SDValue ChainIn = Node->getOperand(0); SDValue Zero = CurDAG->getCopyFromReg(ChainIn, DL, Mips::ZERO, M...

...hort. When this instruction is being translated into x86 machine code, then there is an out of bounds access: ~> llc bug-simple.bc llc: /local/martind/oss/llvm-3.5.0.src/include/llvm/CodeGen/SelectionDAGNodes.h:649: llvm::EVT llvm::SDNode::getValueType(unsigned int) const: Assertion `ResNo < NumValues && "Illegal result number!"' failed. Probably the truncation of NumOperands should be caught directly with an assertion in the SDNode constructor. One other interesting aspect of it is that if you make the struct_2 type a smaller matrix, like: %struct_2 = type { [65534 x %...

...; wrote: > Dear All, > > I currently have one of my transforms creating the following store > instruction: > > store [65536 x i8] zeroinitializer, [65536 x i8]* %buf.i, align 16 > > ... which causes the SelectionDAG code to assert out: > > Assertion failed: (ResNo < NumValues && "Illegal result number!"), > function getValueType, file > /Users/criswell/src/llvm/include/llvm/CodeGen/SelectionDAGNodes.h, line 589. > > Should LLVM be able to code generate the above store instruction?  If > not, how large a value can a store instruction st...

...cause there are several dozens of commits to track on a self-hosting issue (direct compilation goes well), I thought that showing the error on the list would be faster. src/include/llvm/CodeGen/SelectionDAGNodes.h:625: llvm::EVT llvm::SDNode::getValueType(unsigned int) const: Assertion `ResNo < NumValues && "Illegal result number!"' failed. Git blame around that line pointed me at Chris in 2005 and Owen in 2009, which is obviously not what broke the build. Anyone working on that area that have committed recently? Here's one example of a failed build... http://lab.llvm...

...;> I currently have one of my transforms creating the following store >> instruction: >> >> store [65536 x i8] zeroinitializer, [65536 x i8]* %buf.i, align 16 >> >> ... which causes the SelectionDAG code to assert out: >> >> Assertion failed: (ResNo< NumValues&& "Illegal result number!"), >> function getValueType, file >> /Users/criswell/src/llvm/include/llvm/CodeGen/SelectionDAGNodes.h, line 589. >> >> Should LLVM be able to code generate the above store instruction? If >> not, how large a value can a...

On May 24, 2008, at 11:43 AM, Marcel Moolenaar wrote: > All, > > So far I've tried LLVM on amd64, i386, ia64 and powerpc under FreeBSD > and aside for ia64, things look pretty good for a first try. There > are 2 unexpected failures for PowerPC, which appear to be caused by > uninitialized memory. I'm still working on a fix for that (need to > brush up on my C++

All, So far I've tried LLVM on amd64, i386, ia64 and powerpc under FreeBSD and aside for ia64, things look pretty good for a first try. There are 2 unexpected failures for PowerPC, which appear to be caused by uninitialized memory. I'm still working on a fix for that (need to brush up on my C++ skills). [sidenote: In FreeBSD -current, the memory allocator initializes memory with 0xa5

...AIL: /dumpster/home/marcel/LLVM/src/llvm/test/CodeGen/Generic/GC/ frame_size.ll Failed with exit(1) at line 1 while running: llvm-as < /dumpster/home/marcel/LLVM/src/llvm/test/ CodeGen/Generic/GC/frame_size.ll | llc -asm-verbose | grep {frame size} | grep -v 0x0 Assertion failed: (ResNo < NumValues && "Illegal result number!"), function getValueType, file /dumpster/home/marcel/LLVM/src/llvm/ include/llvm/CodeGen/SelectionDAGNodes.h, line 1220. FAIL: /dumpster/home/marcel/LLVM/src/llvm/test/CodeGen/Generic/ 2003-05-27-phifcmpd.ll Failed with signal(SIGABRT) at line 1 w...

.../LLVM/src/llvm/test/CodeGen/Generic/GC/ > frame_size.ll > Failed with exit(1) at line 1 > while running: llvm-as < /dumpster/home/marcel/LLVM/src/llvm/test/ > CodeGen/Generic/GC/frame_size.ll | llc -asm-verbose | grep {frame > size} | grep -v 0x0 > Assertion failed: (ResNo < NumValues && "Illegal result number!"), > function getValueType, file /dumpster/home/marcel/LLVM/src/llvm/ > include/llvm/CodeGen/SelectionDAGNodes.h, line 1220. > > FAIL: /dumpster/home/marcel/LLVM/src/llvm/test/CodeGen/Generic/ > 2003-05-27-phifcmpd.ll > Failed with si...