search for: numregs

...preferred addressing mode. However, it may be deleted because basereg is very likely not to be the most occurred register because the less opportunity in a combination. For the case two, by observing the cost comparison equation bool Cost::operator<(const Cost &Other) const { if (NumRegs != Other.NumRegs) return NumRegs < Other.NumRegs; if (AddRecCost != Other.AddRecCost) return AddRecCost < Other.AddRecCost; if (NumIVMuls != Other.NumIVMuls) return NumIVMuls < Other.NumIVMuls; if (NumBaseAdds != Other....

...rrowSearchSpaceByPickingWinnerRegs, we can preserves the winner reg from target and winner reg from the original algorithm if this function returns NULL, it is just like before For case two, we can define a general cost from TTI function, like virtual int getLSRFormulaCost(const unsigned NumRegs, const unsigned AddRecCost, const unsigned NumIVMuls, const unsigned NumBaseAdds, const unsigned ImmCost, const unsigned SetupCost) const; Then we do something like int thisCost = TTI->getLSRFormulaCost(N...

...ode. However, it may > be deleted because basereg is very likely not to be the most occurred register > because the less opportunity in a combination. > > For the case two, by observing the cost comparison equation > bool Cost::operator<(const Cost &Other) const { > if (NumRegs != Other.NumRegs) return NumRegs < Other.NumRegs; > if (AddRecCost != Other.AddRecCost) return AddRecCost < Other.AddRecCost; > if (NumIVMuls != Other.NumIVMuls) return NumIVMuls < Other.NumIVMuls; > if (NumBaseAd...

...es the winner > > reg from target and winner reg from the original algorithm if this > function > > returns NULL, it is just like before > > > > For case two, we can define a general cost from TTI function, like > > virtual int getLSRFormulaCost(const unsigned NumRegs, > > const unsigned AddRecCost, const unsigned NumIVMuls, > > const unsigned NumBaseAdds, const unsigned ImmCost, > > const unsigned SetupCost) const; > > Then we do something like > > int thisCost = TTI->getLSRFormulaCost(NumRegs, AddRecCost, NumIVMuls, >...

Hi Justin, After catching up with LLVM trunk, I've encountered a new backend issue around i1. Is i1 support still incomplete? Bug report: http://llvm.org/bugs/show_bug.cgi?id=17519 Thanks, - D. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20131009/4ca2cbdd/attachment.html>

...n preserves the winner > > reg from target and winner reg from the original algorithm if this function > > returns NULL, it is just like before > > > > For case two, we can define a general cost from TTI function, like > > virtual int getLSRFormulaCost(const unsigned NumRegs, > > const unsigned AddRecCost, const unsigned > NumIVMuls, > > const unsigned NumBaseAdds, const unsigned > ImmCost, > > const unsigned SetupCost) const; > > Then we do something like...

...RING: %7.4f Volts\n", (float)stats.ringvolt / 1000.0); printf("VBAT: %7.4f Volts\n", (float)stats.batvolt / 1000.0); } } else if (!strcasecmp(argv[2], "regdump")) { struct wctdm_regs regs; int numregs = NUM_REGS; memset(&regs, 0, sizeof(regs)); res = ioctl(fd, WCTDM_GET_REGS, &regs); if (res) { fprintf(stderr, "Unable to get registers on channel %s\n", argv[1]); } else {...

...ddImm(StackSlotForSavedLR)); + + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr)) + .addReg(ARM::LR, RegState::Define) + .addReg(ARM::R4, RegState::Kill)); + } + + MachineInstrBuilder MIB = BuildMI(MF, dl, TII.get(ARM::tPOP)); + AddDefaultPred(MIB); + + bool NumRegs = false; + for (unsigned i = CSI.size(); i != 0; --i) { + unsigned Reg = CSI[i-1].getReg(); + + if (Reg == ARM::LR) + continue; + + MIB.addReg(Reg, getDefRegState(true)); + NumRegs = true; + } + + if (IsR4ToBeAdditionallyAddedToPopIns) { + MIB.addReg(ARM::R4...

...ms that llvm::TargetLowering::getRegForInlineAsmConstraint() is supposed to work on a single (physical) register. In GetRegistersForValue() is the following: 3817 // This is a reference to a register class that doesn't directly correspond 3818 // to an LLVM register class. Allocate NumRegs consecutive, available, 3819 // registers from the class. 3820 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 3821 OpInfo.ConstraintVT); Is it me or is the comment not really applicable to this part...

All, The following IR is causing the assert: \begin{ll} ; ModuleID = 'x.bc' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32- i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64- f80:128:128" target triple = "ia64-portbld-freebsd8.0" define void @__ia64_set_fast_math() nounwind { entry: tail call void asm sideeffect "mov.m

All, This is hopefully the final drop of the patches for adding global heartbeat to the o2cb stack. The diff from the previous set is here: http://oss.oracle.com/~smushran/global-hb-diff-2010-10-07 Implemented most of the suggestions provided by Joel and Wengang. The most important one was to activate the feature only at the end, Also, got mostly a clean run with checkpatch.pl. Sunil