search for: nummicroops

...gt; as helpful during pre-RA scheduling for SystemZ. Could this be made >> optional, or perhaps only done post-RA if target does post-RA >> scheduling? SystemZ does post-RA scheduling to manage decoder >> grouping, which is where the BeginGroup/EndGroup and >> IssueWidth/NumMicroOps is useful. However doing this pre-RA and >> thereby limiting the freedom of other heuristics (making less >> instructions available) seems like a bad idea. > > I've worked on a few cpus in the past that had issue group > restrictions. It seems like a natural way to handl...

Hi, I would like to ask what IssueWidth and NumMicroOps refer to in MachineScheduler, just to be 100% sure what the intent is. Are we modeling the decoder phase or the execution stage? Background: First of all, there seems to be different meanings of "issue" depending on which platform you're on: https://stackoverflow.com/questions/23...

> On May 9, 2018, at 9:43 AM, Jonas Paulsson <paulsson at linux.vnet.ibm.com> wrote: > > Hi, > > I would like to ask what IssueWidth and NumMicroOps refer to in MachineScheduler, just to be 100% sure what the intent is. > Are we modeling the decoder phase or the execution stage? > > Background: > > First of all, there seems to be different meanings of "issue" depending on which platform you're on: > > https...

...eckHazard(), which I actually don't see as helpful during pre-RA scheduling for SystemZ. Could this be made optional, or perhaps only done post-RA if target does post-RA scheduling? SystemZ does post-RA scheduling to manage decoder grouping, which is where the BeginGroup/EndGroup and IssueWidth/NumMicroOps is useful. However doing this pre-RA and thereby limiting the freedom of other heuristics (making less instructions available) seems like a bad idea. I've worked on a few cpus in the past that had issue group restrictions. It seems like a natural way to handle special kinds of instructions. Bu...

...azard(), which I actually don't see as helpful during pre-RA scheduling for SystemZ. Could this be made optional, or perhaps only done post-RA if target does post-RA scheduling? SystemZ does post-RA scheduling to manage decoder grouping, which is where the BeginGroup/EndGroup and IssueWidth/NumMicroOps is useful. However doing this pre-RA and thereby limiting the freedom of other heuristics (making less instructions available) seems like a bad idea. > Sorry, I don't have time to draw diagrams and tables. Hopefully you can makes sense of my long-form rambling. Yes, very helpful to me :-)...

...p;II); llvm::StringRef ref = II.getName(llvm::AArch64::LDADDALX); llvm::MCInstrDesc d = II.get(llvm::AArch64::LDADDALX); printf("name %s; class %d\n", ref.str().c_str(), d.SchedClass); printf("microops %d\n", llvm::ThunderX2T99Model.getSchedClassDesc(d.SchedClass)->NumMicroOps); return 0; } /* LDADDALB_LDADDALH_LDADDALW_LDADDALX = 872, in Sched enum */

...Ref ref = II.getName(llvm::AArch64::LDADDALX); > llvm::MCInstrDesc d = II.get(llvm::AArch64::LDADDALX); > > printf("name %s; class %d\n", ref.str().c_str(), d.SchedClass); > > printf("microops %d\n", llvm::ThunderX2T99Model.getSchedClassDesc(d.SchedClass)->NumMicroOps); > > return 0; > } > > /* > LDADDALB_LDADDALH_LDADDALW_LDADDALX = 872, in Sched enum > */ I bet the problem is that “WriteAtomic” is marked unsupported, so it gets an invalid sched class. The invalid NumMicroOps means that the scheduler will assert if it ever sees that i...

...rch64::LDADDALX); > > llvm::MCInstrDesc d = II.get(llvm::AArch64::LDADDALX); > > > > printf("name %s; class %d\n", ref.str().c_str(), d.SchedClass); > > > > printf("microops %d\n", llvm::ThunderX2T99Model.getSchedClassDesc(d. > SchedClass)->NumMicroOps); > > > > return 0; > > } > > > > /* > > LDADDALB_LDADDALH_LDADDALW_LDADDALX = 872, in Sched enum > > */ > > I bet the problem is that “WriteAtomic” is marked unsupported, so it gets > an invalid sched class. The invalid NumMicroOps means that t...

...d HWPort1 but not HWPort5), then HWPort015 is scheduled according to the round robin scheduler, which in this case would decide to dispatch it on Port5. This (I believe) explains the following reported timings on a basic block which consists of a single instruction with no dependencies and a small NumMicroOps (i.e., only bottlenecked by resource availability), where I have tried out different port maps and ResourceCycles (all of these are for 100 iterations): • When the resource mapping is: { HWPort0: 2 cycles, HWPort01: 2 cycles }, the instruction has a Total Cycles of 200, because the round-robin sch...

...how the Haswell and Broadwell models were originally designed). > > I hope it helps, > -Andrea Food for thought... It would be easy to add a DelayCycles vector to SchedWriteRes to indicate the relative start cycle for each reserved resource. That would effectively model dependent uOps. NumMicroOps is only meant to model any general limitation of the cpu frontend to issue/rename/retire micro-ops. So, yes, there's no way to associate resources with specific uOps. You can mark any kind of resource as "dynamically scheduled" (BufferSize = -1). If an instruction uses different kinds...

...originally designed). > > I hope it helps, > -Andrea > > > Food for thought... > > It would be easy to add a DelayCycles vector to SchedWriteRes to indicate > the relative start cycle for each reserved resource. That would effectively > model dependent uOps. > > NumMicroOps is only meant to model any general limitation of the cpu > frontend to issue/rename/retire micro-ops. So, yes, there's no way to > associate resources with specific uOps. You can mark any kind of resource > as "dynamically scheduled" (BufferSize = -1). If an instruction uses...

Hi Andrew, I seem to be making good progress on the P5600 scheduler using the new machine model but I've got a few questions about it. How would you represent an instruction that splits into two micro-ops and is dispatched to two different reservation stations? For example, I have two reservation stations (AGQ and FPQ). An FPU load instruction is split into a load micro-op which is

...[2] I will assume that each queue is fully pipelined (4 ACQ ops can be in-flight). Forcing all this information into a single SchedWriteRes def would look like this: def P5600FLD : SchedWriteRes <[P5600UnitAGQ, P5600UnitFP]> { let Latency = 5; // 4 cycle load + 1 cycle FP writeback let NumMicroOps = 2; } This is bad (for an in-order processor) because it prevents FPLoad + FPx from being scheduled in the same cycle and fails to detect a conflict on FP ops 5 scheduled cycles ahead. A better way to express it would be: def P5600LD <[P5600UnitAGQ]> { let Latency = 4; } def P5600FP <[...