Displaying 3 results from an estimated 3 matches for "numiterations".
2016 Apr 23
2
[IndVarSimplify] Narrow IV's are not eliminated resulting in inefficient code
Hi Sanjoy,
Thank you for looking into this!
Yes, your patch does fix my larger test case too. My algorithm gets double
performance improvement with the patch, as the loop now has a smaller
instruction set and succeeds to unroll w/o any extra #pragma's.
I also ran the LLVM tests against the patch. There are 6 new failures:
Analysis/LoopAccessAnalysis/number-of-memchecks.ll
2007 Jul 13
0
[LLVMdev] [PATCH] Re: Pluggable Register Coalescers
...quot;
+#include "llvm/CodeGen/RegisterAllocator.h"
+#include "llvm/CodeGen/RegisterCoalescer.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Target/TargetMachine.h"
@@ -47,7 +49,8 @@
static unsigned numIterations = 0;
static unsigned numIntervals = 0;
- struct VISIBILITY_HIDDEN RALinScan : public MachineFunctionPass {
+ struct VISIBILITY_HIDDEN RALinScan : public MachineFunctionPass,
+ public RegisterAllocator {
static char ID;
RALinScan() : MachineFunc...
2007 Jul 11
3
[LLVMdev] Pluggable Register Coalescers
On Jul 11, 2007, at 11:39 AM, David Greene wrote:
> On Wednesday 11 July 2007 12:41, Tanya M. Lattner wrote:
>
>> I think the coalescer should be flexible enough to be run
>> independent of
>> the register allocator. For example, you may want to expose the
>> copies
>> induced by transforming out of SSA to the scheduler. If the
>> scheduler is