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Hi Fellows, Is there a way to allocate dynamic array within an LLVM IR file from my code generator? Say., how to create an array type with a size determined through a global variable. Symbolically, something like below: Value *sz = Mod->getOrInsertGlobal("SIZE", Int32Ty); Type *ArrayTy = ArrayType::get(FloatTy, sz)

...if (EltVT.isInteger()) { // Vectors with a number of elements that is not a power of two are always - // widened, for example <3 x float> -> <4 x float>. + // widened, for example <3 x i8> -> <4 x i8>. if (!VT.isPow2VectorType()) { NumElts = (unsigned)NextPowerOf2(NumElts); EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); + while (!isTypeLegal(NVT)) { + NumElts = (unsigned)NextPowerOf2(NumElts); + NVT = EVT::getVectorVT(Context, EltVT, NumElts); + } return LegalizeKind(TypeWidenV...

...)) { > // Vectors with a number of elements that is not a power of two are always > - // widened, for example <3 x float> -> <4 x float>. > + // widened, for example <3 x i8> -> <4 x i8>. > if (!VT.isPow2VectorType()) { > NumElts = (unsigned)NextPowerOf2(NumElts); > EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); > + while (!isTypeLegal(NVT)) { > + NumElts = (unsigned)NextPowerOf2(NumElts); > + NVT = EVT::getVectorVT(Context, EltVT, NumElts); > + } >...

...< Asghar-ahmad.Shahid at amd.com> wrote: > Hi Zhi, > > > > If I get your question correctly, Yes, you can do it by using the > IRBuilder’s CreateVectorSplat() API. > > > > /// \brief Return a vector value that contains \arg V broadcasted to \p > > /// NumElts elements. > > Value *CreateVectorSplat(unsigned NumElts, Value *V, const Twine &Name = > "") > > > > For your case, here the Value V will be your loaded value %0 and NumElts > will be 2. > > > > So after %0 = load double* %x, align 4, !tbaa !0 &g...

Is it possible to load a value into a vector register and broadcast it in LLVM? For example, for the following address %x %x = getelementptr inbounds %struct._Ray* %ray, i32 0, i32 0, i32 0 instead of loading the value at %x into a scalar register %0: %0 = load double* %x, align 4, !tbaa !0 I want to load it into a <2 x double> vector register %1 and make both of the two elements in %1

...com/llvm-mirror/llvm/tree/master/lib>/CodeGen<https://github.com/llvm-mirror/llvm/tree/master/lib/CodeGen>/TargetLoweringBase.cpp // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we // could break down into LHS/RHS like LegalizeDAG does. if (!isPowerOf2_32(NumElts)) { NumVectorRegs = NumElts; NumElts = 1; } Any suggestions on how to support non-power-of-2-sized vectors? Or maybe a workaround? Thanks, -Kevin -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20...

...const SmallBitVector &Zeroable, const X86Subtarget &Subtarget, SelectionDAG &DAG) { // If we have a single input to the zero element, insert that into V1 if we // can do so cheaply. int NumElts = Mask.size(); int NumV2Elements = count_if(Mask, [NumElts](int M) { return M >= NumElts; }); if (NumV2Elements == 1 && Mask[0] >= NumElts) if (SDValue Insertion = lowerVectorShuffleAsElementInsertion( DL, VT, V1, V2, Mask, Zeroable, Subtarget, DAG)) return...

Hi, We have a function in IRBuilder.h Value *CreateVectorSplat(unsigned NumElts, Value *V, const Twine &Name = "") { .. } This function creates 2 instructions - "insertelement" and "shuffle" with all-zero mask. Now I want to add Value *getSplatValue(Value *Val). This function will try to recognize the pattern - insertelement+shuffle and ret...

...the vector >legalization phase. What I'm looking at is a v3i8 add. In DAGTypeLegalizer::WidenVecRes_Binary the operation gets scalarized (DAG.UnrollVector). The input N is "0x51c1d60: v3i8 = add 0x51c1860, 0x51c1c60 [ORD=5] [ID=0]" and the WidenVT is v4i8. The code ends up in the NumElts == 1 path which causes scalarization. The debug dump shows "Widen node result 0: 0x563dd20: v3i8 = add 0x563d820, 0x563dc20 [ORD=5] [ID=0]". To me it doesn't look like it's possible to both widen and promote an operation.. Paul > >> promoted to v4i32. Why doesn't...

...ion phase. > > What I'm looking at is a v3i8 add. In DAGTypeLegalizer::WidenVecRes_Binary > the operation gets scalarized (DAG.UnrollVector). The input N is > "0x51c1d60: v3i8 = add 0x51c1860, 0x51c1c60 [ORD=5] [ID=0]" and the > WidenVT is v4i8. The code ends up in the NumElts == 1 path which causes > scalarization. > > The debug dump shows "Widen node result 0: 0x563dd20: v3i8 = add > 0x563d820, 0x563dc20 [ORD=5] [ID=0]". To me it doesn't look like it's > possible to both widen and promote an operation.. > > Paul > >>...

...ext, ArrayRef<double> Elts); /// getSplat - Return a ConstantVector with the specified constant in each /// element. The specified constant has to be a of a compatible type (i8/i16/ /// i32/i64/float/double) and must be a ConstantFP or ConstantInt. static Constant *getSplat(unsigned NumElts, Constant *Elt); Cheers, Thomas -----Original Message----- From: Jonathan Roelofs [mailto:jonathan at codesourcery.com] Sent: Thursday, January 15, 2015 6:36 AM To: Raoux, Thomas F; LLVM Developers Mailing List Subject: Re: [LLVMdev] Bug in InsertElement constant propagation? I'm not sure...

Hi Paul, You can read about it here: http://blog.llvm.org/2011/12/llvm-31-vector-changes.html > Hi, > > I am trying to understand how vector type legalization works. In particular, I'm looking at i8 vector types on x86 (with sse42 features) > > v3i8 gets widened to v4i8 and then operations get unrolled (scalarized) because v4i8 is not a legal type whereas v4i8 gets This

...ime error: active field of union 'S::(anonymous union at union-track-active-t1.cpp:2:3)' is 'd'; access to field 'l' is undefined union-track-active-t1.cpp:10:7: note: active index set to 'd' here Runtime functions I've added: struct StringVec { unsigned NumElts; const char *Elts[]; }; struct UnionStaticData { TypeDescriptor *Type; StringVec* FieldNames; }; extern "C" SANITIZER_INTERFACE_ATTRIBUTE void __ubsan_union_set_active_field_index(uptr Addr, const UnionStaticData *Data, const...

...;Width") << ")"; + } else if (ArgType->isSubClassOf("LLVMPackedType")) { + OS << "PackedType::get("; + EmitTypeGenerate(OS, ArgType->getValueAsDef("ElTy")); + OS << ", " << ArgType->getValueAsInt("NumElts") << ")"; + } else { + OS << "Type::getPrimitiveType("; + OS << ArgType->getValueAsString("TypeVal") << ")"; + } +} + /// RecordListComparator - Provide a determinstic comparator for lists of /// records. namespace...

Hi, I am trying to understand how vector type legalization works. In particular, I'm looking at i8 vector types on x86 (with sse42 features) v3i8 gets widened to v4i8 and then operations get unrolled (scalarized) because v4i8 is not a legal type whereas v4i8 gets promoted to v4i32. Why doesn't v3i8 (or even v4i8) get widened to v16i8? Alternatively, v3i8 could be widened to v4i8 then

...d in the vector legalization phase. What I'm looking at is a v3i8 add. In DAGTypeLegalizer::WidenVecRes_Binary the operation gets scalarized (DAG.UnrollVector). The input N is "0x51c1d60: v3i8 = add 0x51c1860, 0x51c1c60 [ORD=5] [ID=0]" and the WidenVT is v4i8. The code ends up in the NumElts == 1 path which causes scalarization. The debug dump shows "Widen node result 0: 0x563dd20: v3i8 = add 0x563d820, 0x563dc20 [ORD=5] [ID=0]". To me it doesn't look like it's possible to both widen and promote an operation.. Paul promoted to v4i32. Why doesn't v3i8 (or even...

I don't see a way to create a ConstantDataVector from Constant or form APFloat though. Did I oversee that? Is the solution to had a new get function in ConstantDataVector to allow that? Any hint on what would be the right fix otherwise? Thomas -----Original Message----- From: Jonathan Roelofs [mailto:jonathan at codesourcery.com] Sent: Wednesday, January 14, 2015 10:30 AM To: Raoux, Thomas

...static VectorType *get(Type *ElementType, ElementCount EC); Type *getElementType() const; ElementCount getElementCount() const; bool isScalable() const; }; class FixedVectorType : public VectorType, public SequentialType { public: static FixedVectorType *get(Type *ElementType, unsigned NumElts); }; class SequentialType : public CompositeType { public: uint64_t getNumElements() const { return NumElements; } }; In this proposed architecture, VectorType does not have a getNumElements() function because it does not inherit from SequentialType. In generic code, users will...

On Mon, 5 Feb 2007, Dan Gohman wrote: > LLVM knows what all the types of the intrinsic functions are; I thought, > why are users (including llvm-gcc...) required to duplicate all this > information in order to use them? I mean in order to call > getOrInsertFunction to get declarations for them. That is an excellent question! :) In the bad old days, we used to allow intrinsics

...;Width") << ")"; + } else if (ArgType->isSubClassOf("LLVMPackedType")) { + OS << "PackedType::get("; + EmitTypeGenerate(OS, ArgType->getValueAsDef("ElTy")); + OS << ", " << ArgType->getValueAsInt("NumElts") << ")"; + } else if (ArgType->isSubClassOf("LLVMPointerType")) { + OS << "PointerType::get("; + EmitTypeGenerate(OS, ArgType->getValueAsDef("ElTy")); + OS << ")"; + } else if (ArgType->isSubClassOf(&quot...