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On Fri, 6 Oct 2006, [UTF-8] Rafael Esp?ndola wrote: > In ARM the stack should be 8 bytes aligned during function calls. A > function that has at least one function call then has a stack size of > 8 bytes. PEI::calculateFrameObjectOffsets corretly computes this > correctly. > > The problem is that the alignment is computed before adding space for > the call frame size. This is

In ARM the stack should be 8 bytes aligned during function calls. A function that has at least one function call then has a stack size of 8 bytes. PEI::calculateFrameObjectOffsets corretly computes this correctly. The problem is that the alignment is computed before adding space for the call frame size. This is done in emitProlog. Currently the ARM backend has a bug in that it doesn't align

...so this is probably the problem. The ARM backend currently doesn't use a frame pointer. It uses the same technique of the PPC backend to avoid add/subs around calls. In the PPC backend we have: ---------------------------------------------------------------------- if (MFI->hasCalls()) { NumBytes += MFI->getMaxCallFrameSize(); } if ((NumBytes == 0) || (NumBytes <= 224 && !HasFP && !MFI->hasCalls() && MaxAlign <= TargetAlign)) { MFI->setStackSize(0); return; } unsigned Align = std::max(TargetAlign, MaxAlign); unsigned GPRSize = 4; un...

...below in case anyone's interested. I wonder what I'm doing wrong.. Appreciate any help, thanks a lot. Mon int PCMToSpx (BSTR FileOpen, BSTR FileSave, bool VAD, short BitRateChoice) { __int8 Speex [6]; __int16 SamplingRate = 8000; __int8 BitsPerSampleX8 = 2 /* ie 2*8=16-bit */, NumBytes /*aka nBytes or nbBytes */; FILE *fin, *fout; void *state; int FrameSize, NumFrames = 0; int BitRate, temp; __int16 in [MaxFrameSize]; __int8 cbits [MaxFrameBytes]; SpeexBits bits; // ********************************** Program Statements *******************************...

...> > '``llvm.webkit.patchpoint.*``' Intrinsic > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ > > Syntax: > """"""" > > :: > > declare void (i32, i32, i8*, i32, ...)* > @llvm.webkit.patchpoint.void(i32 <id>, i32 <numBytes>, i8* <target>, i32 > <numArgs>, ...) > declare i64 (i32, i32, i8*, i32, ...)* > @llvm.webkit.patchpoint.i64(i32 <id>, i32 <numBytes>, i8* <target>, i32 > <numArgs>, ...) > > Overview: > """""""&quo...

...lazy man's conversion speex_bits_reset(m_bits); //preprocess the input //speex_preprocess(m_preprocess, inputptr); //encode speex_encode_int(m_encoderState, inputptr, m_bits); char outputFrame[SPEEX_MAX_ENCODE_SIZE_PER_FRAME]; free(inputptr); unsigned int numBytes = speex_bits_write(m_bits, outputFrame, SPEEX_MAX_ENCODE_SIZE_PER_FRAME); //begin lazy man's conversion to Managed C++ array<Byte>^ output = gcnew array<Byte>(numBytes); for(i = 0; i< numBytes; i++) output[i] = (unsigned char)outputFrame[i]; //end lazy man...

...nge it if one > way works better for you. Hi Chris, Here's the fix: Index: SparcRegisterInfo.cpp =================================================================== --- SparcRegisterInfo.cpp (revision 700) +++ SparcRegisterInfo.cpp (working copy) @@ -137,7 +137,7 @@ if (NumBytes >= -4096) { BuildMI(MBB, MBB.begin(), TII.get(SP::SAVEri), - SP::O6).addImm(NumBytes).addReg(SP::O6); + SP::O6).addReg(SP::O6).addImm(NumBytes); } else { MachineBasicBlock::iterator InsertPt = MBB.begin(); // Emit this the hard way. This clobbers G1 w...

...esponse to an event triggered from outside the code. '``llvm.webkit.patchpoint.*``' Intrinsic ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Syntax: """"""" :: declare void (i32, i32, i8*, i32, ...)* @llvm.webkit.patchpoint.void(i32 <id>, i32 <numBytes>, i8* <target>, i32 <numArgs>, ...) declare i64 (i32, i32, i8*, i32, ...)* @llvm.webkit.patchpoint.i64(i32 <id>, i32 <numBytes>, i8* <target>, i32 <numArgs>, ...) Overview: """"""""" The '``llvm.webkit.p...

...t; > > '``llvm.webkit.patchpoint.*``' Intrinsic > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ > > Syntax: > """"""" > > :: > > declare void (i32, i32, i8*, i32, ...)* > @llvm.webkit.patchpoint.void(i32 <id>, i32 <numBytes>, i8* <target>, > i32 <numArgs>, ...) > declare i64 (i32, i32, i8*, i32, ...)* > @llvm.webkit.patchpoint.i64(i32 <id>, i32 <numBytes>, i8* <target>, > i32 <numArgs>, ...) > > Overview: > """"""""&qu...

...aving IRGen introduce a "thunk" function in the case when ::operator new has its address taken? For example, you could have this pseudo code: auto FP = & ::operator new; // I have no idea how to actually spell this in C++ IRGen into the equivalent of: static void *thunk(size_t NumBytes) { return ::operator new(NumBytes); // Direct call, with nobuiltin attribute set. } auto FP = thunk; That way the pain of this corner case is hoisted into clang, instead of subjecting all consumers of LLVM IR to a complexity increase. -Chris -------------- next part -------------- An HTML...

...er/callee cleans arguments off the stack" is not controlled by the .td. It's controlled in code by the operands of CALLSEQ_END. for example in SDOperand X86TargetLowering::LowerCCCCallTo: ... if (CC == CallingConv::X86_StdCall || CC == CallingConv::Fast) { if (isVarArg) NumBytesForCalleeToPush = isSRet ? 4 : 0; else NumBytesForCalleeToPush = NumBytes; assert(!(isVarArg && CC==CallingConv::Fast) && "CallingConv::Fast does not support varargs."); } else { // If this is is a call to a struct-return function, the...

On Jul 31, 2008, at 9:57 AM, Dale Johannesen wrote: > > On Jul 31, 2008, at 4:52 AMPDT, Richard Pennington wrote: > >> Any code that I generate for the Sparc fails at assembly time using a >> gas assembler built for the Sparc. >> >> I get code like the following from the code generator: >> >> save -96, %o6, %o6 >> >> and get a syntax

...n-varargs Altivec parameters go after all the non-Altivec + // parameters; handle those later so we know how much padding we need. + nAltivecParamsAtEnd++; + continue; + } else { + // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary. + NumBytes = ((NumBytes+15)/16)*16; + } => + if (!isVarArg && !isPPC64) { + // Non-varargs Altivec parameters go after all the non-Altivec + // parameters; handle those later so we know how much padding we need. + nAltivecParamsAtEnd++; + continue; + }...

...eMappedMemory() is called to reserve memory. If the distance between the pointers gets too large, then the test case fails. It can be reliable produced with a distance of 1MB between the pointers. An easy way to simulate this is to increase the number of memory bytes requested by 1MB (e.g. adding NumBytes += (1<<20); at begin of the method). Then the check if a relocation is correctly resolved fails. My current understanding is that the kernel is more or less free to choose the address of the mapped memory, so this situation can arise. Is this true, or do I miss something? Sorry if this is...

...:119 #2 0x0000000000402fe0 in nfct_helper_cb (nlh=nlh at entry=0x7fffffffc9d0, data=data at entry=0x0) at nfct-extensions/helper.c:113 #3 0x00007ffff7bd9370 in __mnl_cb_run (cb_ctl_array_len=0, cb_ctl_array=0x0, data=0x0, cb_data=0x402f80 <nfct_helper_cb>, portid=22283, seq=1418033670, numbytes=4206464, buf=0x7fffffffc9d0) at callback.c:71 #4 mnl_cb_run (buf=buf at entry=0x7fffffffc9d0, numbytes=numbytes at entry=112, seq=seq at entry=1418033670, portid=portid at entry=22283, cb_data=cb_data at entry=0x402f80 <nfct_helper_cb>, data=data at entry=0x0) at callback.c:155 #5 0x00...

Hello Dale, this is an updated version of the tail call optimization patch for powerpc. could you have a look at it? i added code to support ppc64 (untested, will try to get access to ppc64 on a friend's machine). incorporated evan's formatting suggestions. ;) will run another round of testing (llvm-test) on my powerpc g4/800 when i get the okay to commit. testing on this machine takes

...entry=0x3cc19166b30, data=data at entry=0x3cc19177bd0) at netlink.c:2464 ret = 1 type = 17 monh = 0x3cc19177bd0 #5 0x000003c19109b490 in __mnl_cb_run (cb_ctl_array_len=0, cb_ctl_array=0x0, data=0x3cc19177bd0, cb_data=0x47a6a07530 <netlink_events_cb>, portid=0, seq=0, numbytes=420899556, buf=0x3cc19166ad0) at callback.c:78 ret = 1 len = 176 nlh = 0x3cc19166b30 #6 mnl_cb_run (buf=buf at entry=0x3cc19166b30, numbytes=numbytes at entry=176, seq=seq at entry=0, portid=portid at entry=0, cb_data=cb_data at entry=0x47a6a07530 <netlink_events_cb>,...

...lling values out of > the accumulator, you do that based upon the number of bits > requested. The accumulator will have to be (long long) because you > will sometimes request more than 32 bits. > > In other words, instead of: > > GetEndianBytes(streamArray, streamOffset, numBytes); > > ... you should implement: > > (long long)GetBigEndianStreamBits(streamHandle, (unsigned)numBits); > > The return value will have to be 64-bit to handle totalSamples. > The nice thing is that you won't need any indexing or bit shifting, > because GetBigEndianSt...

...tchpoint.*``' Intrinsic >> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ >> >> Syntax: >> """"""" >> >> :: >> >> declare void (i32, i32, i8*, i32, ...)* >> @llvm.webkit.patchpoint.void(i32 <id>, i32 <numBytes>, i8* <target>, >> i32 <numArgs>, ...) >> declare i64 (i32, i32, i8*, i32, ...)* >> @llvm.webkit.patchpoint.i64(i32 <id>, i32 <numBytes>, i8* <target>, >> i32 <numArgs>, ...) >> >> Overview: >> """&quot...

...to display and do anything with a variable of type IntrinsicInst, gdb thinks that it's an incomplete type and kind find any member functions or even display the class. (gdb) list 1337 1332 1333 // Finish off the call including any return values. 1334 return finishCall(CLI, RetVT, NumBytes); 1335 } 1336 1337 bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) { 1338 switch (II->getIntrinsicID()) { 1339 default: 1340 return false; 1341 case Intrinsic::bswap: { (gdb) print II $10 = (const llvm::IntrinsicInst *) 0x61b8ec8 (gdb) print *II $11...