Displaying 3 results from an estimated 3 matches for "nshld".
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2016 Jan 13
4
RFC: non-temporal fencing in LLVM IR
...ecified as a specific instruction.
*Is it safe to access top-of-stack?*
AFAIK yes, and the ABI-specified red zone has our back (or front if the
stack grows up ☻).
*What about non-x86 architectures?*
Architectures such as ARMv8 support non-temporal instructions and require
barriers such as DMB nshld to order loads and DMB nshst to order stores.
Even ARM's address-dependency rule (a.k.a. the ill-fated
std::memory_order_consume) fails to hold with non-temporals:
LDR X0, [X3]
LDNP X2, X1, [X0] // X0 may not be loaded when the instruction executes!
*Who uses non-temporals anyways?*
That&...
2016 Jan 13
2
RFC: non-temporal fencing in LLVM IR
On Wed, Jan 13, 2016 at 10:32 AM, John Brawn <John.Brawn at arm.com> wrote:
> *What about non-x86 architectures?*
>
>
>
> Architectures such as ARMv8 support non-temporal instructions and require
> barriers such as DMB nshld to order loads and DMB nshst to order stores.
>
>
>
> Even ARM's address-dependency rule (a.k.a. the ill-fated
> std::memory_order_consume) fails to hold with non-temporals:
>
> LDR X0, [X3]
>
> LDNP X2, X1, [X0] // X0 may not be loaded when the instruction executes!...
2016 Jan 14
2
RFC: non-temporal fencing in LLVM IR
...f-stack?
>
> > AFAIK yes, and the ABI-specified red zone has our back (or front if
> > the stack grows up ☻).
>
> > What about non-x86 architectures?
>
> > Architectures such as ARMv8 support non-temporal instructions and
> > require barriers such as DMB nshld to order loads and DMB nshst to
> > order stores.
>
> > Even ARM's address-dependency rule (a.k.a. the ill-fated
> > std::memory_order_consume ) fails to hold with non-temporals:
>
> > > LDR X0, [X3]
> >
>
> > > LDNP X2, X1, [X0] // X0 m...