Displaying 6 results from an estimated 6 matches for "nreplac".
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nreplace
2010 Oct 03
2
How to programme R to randomly replace some X values with Outliers
Dear experts,
I am a beginner of R.
I'm looking for experts to guide me how to do programming in R in order to
randomly replace 5 observations in X explanatory variable with outliers drawn
from U(15,20) in sample size n=100. The replacement subject to y < 15.
The ultimate goal of my study is to compare the std of y with and without the
presence of outliers based on average of 1000
2010 Oct 02
1
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
...getOperand(1);
>> if (Op0.getOpcode() == Op1.getOpcode()) {
>> // Avoid missing important xor optimizations.
>> SDValue Tmp = visitXOR(TheXor);
>> if (Tmp.getNode()&& Tmp.getNode() != TheXor) {
>> DEBUG(dbgs()<< "\nReplacing.8 ";
>> TheXor->dump(&DAG);
>> dbgs()<< "\nWith: ";
>> Tmp.getNode()->dump(&DAG);
>> dbgs()<< '\n');
>> WorkListRemover DeadNodes(*this);
>>...
2010 Sep 30
4
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
...getOperand(0);
SDValue Op1 = TheXor->getOperand(1);
if (Op0.getOpcode() == Op1.getOpcode()) {
// Avoid missing important xor optimizations.
SDValue Tmp = visitXOR(TheXor);
if (Tmp.getNode() && Tmp.getNode() != TheXor) {
DEBUG(dbgs() << "\nReplacing.8 ";
TheXor->dump(&DAG);
dbgs() << "\nWith: ";
Tmp.getNode()->dump(&DAG);
dbgs() << '\n');
WorkListRemover DeadNodes(*this);
DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &...
2010 Oct 01
0
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
...SDValue Op1 = TheXor->getOperand(1);
> if (Op0.getOpcode() == Op1.getOpcode()) {
> // Avoid missing important xor optimizations.
> SDValue Tmp = visitXOR(TheXor);
> if (Tmp.getNode() && Tmp.getNode() != TheXor) {
> DEBUG(dbgs() << "\nReplacing.8 ";
> TheXor->dump(&DAG);
> dbgs() << "\nWith: ";
> Tmp.getNode()->dump(&DAG);
> dbgs() << '\n');
> WorkListRemover DeadNodes(*this);
> DAG.ReplaceAllUsesOf...
2010 Sep 29
0
[LLVMdev] comparison pattern trouble - might be a bug in LLVM 2.8?
On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote:
> On 29 Sep 2010, at 06:25, Heikki Kultala wrote:
>
>> Our architecture has 1-bit boolean predicate registers.
>>
>> I've defined comparison
>>
>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;
2010 Sep 29
1
[LLVMdev] comparison pattern trouble - might be a bug in LLVM 2.8?
On 29 Sep 2010, at 06:25, Heikki Kultala wrote:
> Our architecture has 1-bit boolean predicate registers.
>
> I've defined comparison
>
>
> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;
>
>
>
>
> But then I end up having the following bug:
>
>