Displaying 7 results from an estimated 7 matches for "nr_pstate".
Did you mean:
nr_pstates
2016 Apr 18
0
[PATCH v4 31/37] clk: split out update code to nv40
...v/clk/gk20a.c
index 5f0ee24..8b64cc9 100644
--- a/drm/nouveau/nvkm/subdev/clk/gk20a.c
+++ b/drm/nouveau/nvkm/subdev/clk/gk20a.c
@@ -636,6 +636,7 @@ gk20a_clk = {
.calc = gk20a_clk_calc,
.prog = gk20a_clk_prog,
.tidy = gk20a_clk_tidy,
+ .update = nv40_clk_update,
.pstates = gk20a_pstates,
.nr_pstates = ARRAY_SIZE(gk20a_pstates),
.domains = {
diff --git a/drm/nouveau/nvkm/subdev/clk/gm20b.c b/drm/nouveau/nvkm/subdev/clk/gm20b.c
index 71b2bbb..8c8eb8c 100644
--- a/drm/nouveau/nvkm/subdev/clk/gm20b.c
+++ b/drm/nouveau/nvkm/subdev/clk/gm20b.c
@@ -168,6 +168,7 @@ gm20b_clk_speedo0 = {
.calc = g...
2016 Apr 18
0
[PATCH v4 35/37] clk: set clocks to pre suspend state after suspend
...7 @@ struct nvkm_clk_func {
int (*calc)(struct nvkm_clk *, struct nvkm_cstate *);
int (*prog)(struct nvkm_clk *);
void (*tidy)(struct nvkm_clk *);
- void (*update)(struct nvkm_clk *, int pstate);
+ void (*update)(struct nvkm_clk *, int pstate, bool force);
struct nvkm_pstate *pstates;
int nr_pstates;
struct nvkm_domain domains[];
@@ -30,6 +30,6 @@ int nv04_clk_pll_calc(struct nvkm_clk *, struct nvbios_pll *, int clk,
struct nvkm_pll_vals *);
int nv04_clk_pll_prog(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *);
-void nv40_clk_update(struct nvkm_clk *, int pstate);
-void gf1...
2016 Jun 01
15
[PATCH 00/15] clk/tegra: improve code and add DFS support
This series adds support for GM20B PLL's Maxwell features, namely glitchless
switch and (more importantly) DFS support. DFS lets the PLL lower its output
speed according to input current variations, making the clock more stable and
allowing it to run safely at lower voltage.
All GM20B additions are done in the last patch, which consequently ends up
being considerably big ; fortunately, it
2017 Mar 05
15
[PATCH 0/9] clk subdev updates
This series addresses various issues inside the reclocking code:
1. after resume the set clocks are reset
2. reclocking not possible while GPU is suspended
3. nouveau always does full reclocks even if only a change of the voltage is
required
Some of the patches were part of the bigger reclocking series I sent months
ago, some things have changed though.
This is also preparation work of
2017 Nov 17
35
[PATCH 00/32] Updated State of my clk patches
Last update here: https://lists.freedesktop.org/archives/nouveau/2017-September/028848.html
Basically big cleanup, reordering, simplifications and some renaming to make
the code easier to read and to review. I also moved some bugfixes to the front
so they can be merged prior the other patches.
There was also a bug related to the therm daemon triggering a pstate change
leading to PMU lockups,
2016 Apr 18
63
[PATCH v4 00/37] Volting/Clocking improvements for Fermi and newer
We are slowly getting there!
v4 of the series with some realy good improvements, so I am sure this is like
95% done and only needs some proper polishing and proper Reviews!
I also added the NvVoltOffsetmV module parameter, so that a user is able to
over and !under!-volt the GPU. Overvolting makes sense, when there are still
some reclocking issues left, which might be solved by a higher voltage.
2016 Mar 11
16
[PATCH 00/16] clk/gm20b: add basic driver
This series does some refactoring in the GK20A's volt and clk drivers
(fixing a few things while we are at it) to let GM20B benefit from the
GK20A's logic with which it is compatible.
GM20B is capable of more sophisticated (and power-efficient) reclocking
which will follow later. Even after this more fancy reclocking is merged,
the present logic will remain used in the lowest speedo of