search for: nr_dwords

Signed-off-by: Pekka Paalanen <pq at iki.fi> --- drivers/gpu/drm/nouveau/nouveau_gem.c | 7 ++++--- 1 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index 64e59fb..75cae79 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c @@ -595,7 +595,7 @@

...al_suffix0; + *(chan->cur++) = nvpb->cal_suffix1; restart_cal: req.channel = chan->id; @@ -208,7 +204,7 @@ restart_cal: req.buffers = (uint64_t)(unsigned long)nvpb->buffers; req.nr_relocs = nvpb->nr_relocs; req.relocs = (uint64_t)(unsigned long)nvpb->relocs; - req.nr_dwords = (nvpb->base.cur - nvpb->pushbuf) - + req.nr_dwords = (chan->cur - nvpb->pushbuf) - nvpb->current_offset; req.suffix0 = nvpb->cal_suffix0; req.suffix1 = nvpb->cal_suffix1; @@ -229,7 +225,7 @@ restart_cal: restart_push: req.channel = chan->id; - req.nr_dwo...

Revised patch set v2. [PATCH 1/8] drm/nouveau: bo read/write wrappers for nv04_crtc.c [PATCH 2/8] drm/nouveau: use bo accessors for push buffers [PATCH 3/8] drm/nouveau: OUT_RINGp - optimize OUT_RING loops [PATCH 4/8] drm/nv50: proper notifier_bo access in nv50_display_vblank_crtc_handler() [PATCH 5/8] drm/nouveau: access fbcon notifier via bo accessors [PATCH 6/8] drm/nouveau: screen_base and

...gem_pushbuf_bo *bo = NULL; struct nouveau_channel *chan; struct validate_op op; + struct nouveau_fence* fence = 0; uint32_t *pushbuf = NULL; int ret = 0, do_reloc = 0, i; @@ -597,7 +587,8 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data, OUT_RINGp(chan, pushbuf, req->nr_dwords); - ret = nouveau_fence_emit(op.fence); + ret = nouveau_fence_new(chan, &fence, false) + || nouveau_fence_emit(fence); if (ret) { NV_ERROR(dev, "error fencing pushbuf: %d\n", ret); WIND_RING(chan); @@ -605,7 +596,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *...

Hello, I have my work on the nv vpe video decoder in a functional state. In case you didn't know this decoder accelerates mpeg2 video at the idct/mc level. I have verified that it works on nv40 hardware. I believe it works on nv30 hardware (and maybe some earlier hardware), but I cannot verify since I have none. I will reply with patches against the kernel, drm, ddx and mesa for