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Thanks, that did it! Are there any plans to enable the loop vectorizer by default? From: Nadav Rotem [mailto:nrotem at apple.com] Sent: Wednesday, April 03, 2013 13:33 PM To: Nowicki, Tyler Cc: LLVM Developers Mailing List Subject: Re: Packed instructions generaetd by LoopVectorize? Hi Tyler, Try adding -ffast-math. We can only vectorize reduction variables if it is safe to reorder floating point operations. Thanks, Nadav On Apr 3, 2013, at 10:29 AM, "Nowicki, Tyler&q...

On Thu, Feb 21, 2013 at 12:14 PM, Nadav Rotem <nrotem at apple.com> wrote: > You can change the input LLVM-IR. > > On Feb 21, 2013, at 7:16 AM, "Nowicki, Tyler" <tyler.nowicki at intel.com> > wrote: > > Hi,**** > > ** ** > > I am interested in evaluating the performance of packed vs scalar > double-precision floating point instructions on x86-atom and I was > wondering if anyone knows more precisely where to m...

...much more difficult to detect when a real 32-bit divide is happening. If someone knows where the 8-bit DIV is being handled in the IR I could look into this change? Tyler -----Original Message----- From: Eli Friedman [mailto:eli.friedman at gmail.com] Sent: Wednesday, June 27, 2012 19:07 PM To: Nowicki, Tyler Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] 8-bit DIV IR irregularities On Wed, Jun 27, 2012 at 4:02 PM, Nowicki, Tyler <tyler.nowicki at intel.com> wrote: > Hi, > > > > I noticed that when dividing with signed 8-bit values the IR uses a > 32-bit signed divide...

...signed char b) { unsigned char c = a / b; return c; } define zeroext i8 @div8(i8 zeroext %a, i8 zeroext %b) nounwind readnone { entry: %div3 = udiv i8 %a, %b ret i8 %div3 } I noticed the same behavior in O3. The command line arguments I'm using for clang are: -O2 -emit-llvm -S. Tyler Nowicki Intel -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120627/e47dfdcd/attachment.html>

Hi Tyler, Try adding -ffast-math. We can only vectorize reduction variables if it is safe to reorder floating point operations. Thanks, Nadav On Apr 3, 2013, at 10:29 AM, "Nowicki, Tyler" <tyler.nowicki at intel.com> wrote: > Hi, > > I have a question about LoopVectorize. I wrote a simple test case, a dot product loop and found that packed instructions are generated when input arrays are integer, but not when they are float or double. > > If I...

Was there any development on this? I noticed that clang still produces a lea for the testcase in llvm.org/pr13320. On 28 September 2012 11:36, Nowicki, Tyler <tyler.nowicki at intel.com> wrote: > Hi, > > > > Here is an update on our proposal to improve the uses of LEA on Atom > processors. > > > > 1. Disable current generation of LEAs > > > > Due to a 3 cycle stall between the ALU and the AGU any ad...

...prevent BBVectorize from packing together double precision instructions? If a non-clang frontend is used, such as ISPC, is it possible that the IR may contain packed double instruction? Tyler From: Cameron McInally [mailto:cameron.mcinally at nyu.edu] Sent: Thursday, February 21, 2013 6:39 PM To: Nowicki, Tyler Cc: Nadav Rotem; LLVM Developers Mailing List Subject: Re: [LLVMdev] Generate scalar SSE instructions instead of packed instructions On Thu, Feb 21, 2013 at 12:14 PM, Nadav Rotem <nrotem at apple.com<mailto:nrotem at apple.com>> wrote: You can change the input LLVM-IR. On Feb 2...

...ocation it will not affect instruction scheduling. Attached is an incomplete patch with test cases that disables current LEA generation and includes an empty pre-emit pass that will contain the LEA selection heuristics. Any feedback you may have on this updated plan is welcome. Sincerely, Tyler Nowicki Intel -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120928/cfbf8bf3/attachment.html> -------------- next part -------------- A non-text attachment was scrubbed... Name: UpdatedProposalPatch-svn.patch Typ...

On Wed, Jun 27, 2012 at 4:02 PM, Nowicki, Tyler <tyler.nowicki at intel.com> wrote: > Hi, > > > > I noticed that when dividing with signed 8-bit values the IR uses a 32-bit > signed divide, however, when unsigned 8-bit values are used the IR uses an > 8-bit unsigned divide. Why not use a 8-bit signed divide when...

Hi, I have a question about LoopVectorize. I wrote a simple test case, a dot product loop and found that packed instructions are generated when input arrays are integer, but not when they are float or double. If I modify the float example in http://llvm.org/docs/Vectorizers.html by adding restrict to the input arrays packed instructions are generated. Although it should not be required I tried

You can change the input LLVM-IR. On Feb 21, 2013, at 7:16 AM, "Nowicki, Tyler" <tyler.nowicki at intel.com> wrote: > Hi, > > I am interested in evaluating the performance of packed vs scalar double-precision floating point instructions on x86-atom and I was wondering if anyone knows more precisely where to modify llvm to use one or the other. I...

On Wed, Jun 27, 2012 at 5:22 PM, Nowicki, Tyler <tyler.nowicki at intel.com> wrote: > I understand, but this sounds like legalization. Does every architecture trigger an overflow exception, as opposed to setting a bit? Perhaps it makes more sense to do this in the backends that trigger an overflow exception? The IR instruction h...

Hi, I am interested in evaluating the performance of packed vs scalar double-precision floating point instructions on x86-atom and I was wondering if anyone knows more precisely where to modify llvm to use one or the other. I know I probably need to change something in the type legalizer. Could anyone provide more details than that? Thanks, Tyler -------------- next part -------------- An HTML

...VM and not sure how to do this. I've been trying to find where the mov esp->reg instructions are generated but I haven't had much luck. Could anyone point me in the right direction? Or suggest an another approach for solving this problem? Comments and suggestions are appreciated, Tyler Nowicki Software Developer Intel Corporation -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20111124/e8580239/attachment.html>

On Thu, Nov 24, 2011 at 11:39:32AM -0700, Nowicki, Tyler wrote: > When compiled for atom with clang in 32-bit mode the 8-bit variables > in test use 32-bit registers: That's fine since it can avoid partial stales and the value of the padding is undefined. > However, the 8-bit variables in PartialRegisterOperationsTestChar use > 8...

Hi , I have a test case (and a micro benchmark made out of the test case) to check if loop unrolling and loop vectorization is efficiently done on LLVM. Here is the test case (credits: Tyler Nowicki) {code} extern float * array; extern int array_size; float g() { int i; float total = 0; for(i = 0; i < array_size; i++) { total += array[i]; } return total; } {code} When compiled with the options -m32 -mfpmath=sse -ffast-math -funroll-loops -O3 -march=atom for gcc, and cla...

...EmitInstrWithCustomInserter). However, the isel already done in X86ISelDAGToDAG, line 2200, adds multiple instructions which makes adding control flow in X86ISelLowering difficult. Also, it looks like control flow cannot be added in X86ISelDAGToDAG. Any suggestions are appreciated. Thanks, Tyler Nowicki Intel -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120618/06d1384d/attachment.html>

> On May 16, 2016, at 5:35 PM, Hal Finkel via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > ----- Original Message ----- >> From: "Sanjoy Das via llvm-dev" <llvm-dev at lists.llvm.org> >> To: escha at apple.com >> Cc: "llvm-dev" <llvm-dev at lists.llvm.org>, "Michael V Zolotukhin" <michael.v.zolotukhin at

Hi Tyler, > -Does anyone know where a backend-specific optimization can be added to replace > an instruction with code containing control flow? I think the backend lowering of atomic intrinsics generates control flow (loops), so that may give you a clue. Ciao, Duncan.

...due to a 3 cycle stall between the execution stage and the address generator. Attached is an incomplete patch that disables isel LEA generation and includes an empty pre-emit pass that will contain the LEA selection heuristics. Any feedback you may have on this plan is welcome. Sincerely, Tyler Nowicki Intel -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120810/3697e3c9/attachment.html> -------------- next part -------------- A non-text attachment was scrubbed... Name: UseEarlyAG_Template_svn.patch Type...