Displaying 5 results from an estimated 5 matches for "now1".
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2018 Sep 18
3
[patch 09/11] x86/vdso: Simplify the invalid vclock case
On Tue, Sep 18, 2018 at 12:41:57PM +0200, Thomas Gleixner wrote:
> On Tue, 18 Sep 2018, Thomas Gleixner wrote:
> > On Tue, 18 Sep 2018, Thomas Gleixner wrote:
> > > On Tue, 18 Sep 2018, Peter Zijlstra wrote:
> > > > > Your memory serves you right. That's indeed observable on CPUs which
> > > > > lack TSC_ADJUST.
> > > >
> >
2018 Sep 18
3
[patch 09/11] x86/vdso: Simplify the invalid vclock case
On Tue, Sep 18, 2018 at 12:41:57PM +0200, Thomas Gleixner wrote:
> On Tue, 18 Sep 2018, Thomas Gleixner wrote:
> > On Tue, 18 Sep 2018, Thomas Gleixner wrote:
> > > On Tue, 18 Sep 2018, Peter Zijlstra wrote:
> > > > > Your memory serves you right. That's indeed observable on CPUs which
> > > > > lack TSC_ADJUST.
> > > >
> >
2010 Oct 28
1
Unexpected behabiour of min, tapply and POSIXct/POSIXlt classes?
Hello,
I found rather surprising the behaviour of POSIXct and POSIXlt classes
when combined with min and tapply.
The details can be deduced from the script below:
############# Start of the script ####################
before <- Sys.time()
Sys.sleep( 1 )
now1 <- now2 <- Sys.time()
my.times <- c( before, now1, now2 )
class( my.times ) ## [1] "POSIXct" "POSIXt"
min( my.times ) ## [1] "2010-10-28 18:52:17 CEST"
### So far, so good... but:
my.period <- c( "a", "b", "b" )
ta...
2018 Sep 18
0
[patch 09/11] x86/vdso: Simplify the invalid vclock case
...reorder? Because if I look at the
> current code:
The load order of last vs. rdtsc does not matter at all.
CPU0 CPU1
....
now0 = rdtsc_ordered();
...
tk->cycle_last = now0;
gtod->seq++;
gtod->cycle_last = tk->cycle_last;
...
gtod->seq++;
seq_begin(gtod->seq);
now1 = rdtsc_ordered();
So if the TSC on CPU1 is slightly behind the TSC on CPU0 then now1 can be
smaller than cycle_last. The TSC sync stuff does not catch the small delta
for unknown raisins. I'll go and find that machine and test that again.
Thanks,
tglx
2018 Sep 18
1
[patch 09/11] x86/vdso: Simplify the invalid vclock case
On Tue, 18 Sep 2018, Thomas Gleixner wrote:
> So if the TSC on CPU1 is slightly behind the TSC on CPU0 then now1 can be
> smaller than cycle_last. The TSC sync stuff does not catch the small delta
> for unknown raisins. I'll go and find that machine and test that again.
Of course it does not trigger anymore. We accumulated code between the
point in timekeeping_advance() where the TSC is read and th...