search for: nouveau_pst

...eau_noaccel); + DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset); + DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm); + DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf); + DRM_DEBUG_DRIVER("... pstate : %d\n", nouveau_pstate); +} + static const struct dev_pm_ops nouveau_pm_ops = { .suspend = nouveau_pmops_suspend, .resume = nouveau_pmops_resume, @@ -1085,6 +1103,8 @@ EXPORT_SYMBOL(nouveau_platform_device_create_); static int __init nouveau_drm_init(void) { + nouveau_display_options(); + if (nouveau_modeset...

I made a little changes in this series: 1. merge the two last patches together 2. unify the private data interface with the drm debugfs one now it should be very obvious for a new dev on how to add new files to debugfs and how to get access to the nouveau structs Karol Herbst (5): debugfs: add infrastructure to add files with other fops than only read debugfs: rename functions to

...6 +1032,7 @@ static void nouveau_display_options(void) > DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm); > DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf); > DRM_DEBUG_DRIVER("... pstate : %d\n", nouveau_pstate); > + DRM_DEBUG_DRIVER("... staging : %d\n", nouveau_staging); > } > > static const struct dev_pm_ops nouveau_pm_ops = { > @@ -1088,6 +1094,18 @@ err_free: > static int __init > nouveau_drm_init(void) > { > + /* Do not register staging i...

...nouveau_display_options(void) >>> DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm); >>> DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf); >>> DRM_DEBUG_DRIVER("... pstate : %d\n", nouveau_pstate); >>> + DRM_DEBUG_DRIVER("... staging : %d\n", nouveau_staging); >>> } >>> >>> static const struct dev_pm_ops nouveau_pm_ops = { >>> @@ -1088,6 +1094,18 @@ err_free: >>> static int __init >>> nouveau_drm_init...

This patchset proposes to introduce a "staging" module option to dynamically enable features (mostly ioctls) that are merged but may be refined before they are declared "stable". The second patch illustrates the use of this staging option with the SET_TILING ioctl, which can be used to specify the tiling options of a PRIME-imported buffer. The staging parameter will allow us

Second version of this patchset addressing Ben's comments and fixing a few extra things. This patchset proposes to introduce a "staging" module option to dynamically enable features (mostly ioctls) that are merged but may be refined before they are declared "stable". The second patch illustrates the use of this staging option with the SET_TILING ioctl, which can be used to

Second version of the gk20a clock patches. I have tried to keep the therm and volt devices mandatory in the clock driver, but unfortunately they are too tied to bios to allow this, at least for the moment. Consequently this version is mostly a port of the first version to Ben's tree. Ben, please let me know what I have done wrong in terms of integration to your tree, as the main purpose of

...#define _nouveau_clock_fini _nouveau_subdev_fini diff --git a/nvkm/subdev/clock/base.c b/nvkm/subdev/clock/base.c index dd62bae..80ad9d3 100644 --- a/nvkm/subdev/clock/base.c +++ b/nvkm/subdev/clock/base.c @@ -346,8 +346,8 @@ nouveau_clock_ustate_update(struct nouveau_clock *clk, int req) struct nouveau_pstate *pstate; int i = 0; - /* YKW repellant */ - return -ENOSYS; + if (!clk->allow_reclock) + return -ENOSYS; if (req != -1 && req != -2) { list_for_each_entry(pstate, &clk->states, head) { @@ -456,6 +456,7 @@ nouveau_clock_create_(struct nouveau_object *parent,...

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Hope I understood you correctly wrt the mem exec stuff. nvkm/subdev/fb/ramnv50.c | 2 +- nvkm/subdev/fb/ramnva3.c | 2 +- nvkm/subdev/fb/ramnvc0.c | 2 +- nvkm/subdev/fb/ramnve0.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/nvkm/subdev/fb/ramnv50.c b/nvkm/subdev/fb/ramnv50.c index ef91b6e..e5d12c2 100644

...u_subdev_fini > diff --git a/nvkm/subdev/clock/base.c b/nvkm/subdev/clock/base.c > index dd62bae..80ad9d3 100644 > --- a/nvkm/subdev/clock/base.c > +++ b/nvkm/subdev/clock/base.c > @@ -346,8 +346,8 @@ nouveau_clock_ustate_update(struct nouveau_clock *clk, int req) > struct nouveau_pstate *pstate; > int i = 0; > > - /* YKW repellant */ > - return -ENOSYS; > + if (!clk->allow_reclock) > + return -ENOSYS; > > if (req != -1 && req != -2) { > list_for_each_entry(pstate, &clk->...

This series adds support for reclocking on GK20A. The first two patches touch the clock subsystem to allow GK20A to operate, by making the presence of the thermal and voltage devices optional, and allowing pstates to be provided directly instead of being probed using the BIOS (which Tegra does not have). The last patch adds the GK20A clock device. Arguably the clock can be seen as a stripped-down

...IT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0); + + _gk20a_pllg_disable(priv); +} + +#define GK20A_CLK_GPC_MDIV 1000 + +static struct nouveau_clocks +gk20a_domains[] = { + { nv_clk_src_crystal, 0xff }, + { nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV }, + { nv_clk_src_max } +}; + +static struct nouveau_pstate +gk20a_pstates[] = { + { + .base = { + .domain[nv_clk_src_gpc] = 72000, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 108000, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 180000, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 252000, + }, + }, + { + .base...

...> @@ -1029,6 +1034,7 @@ static void nouveau_display_options(void) > DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm); > DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf); > DRM_DEBUG_DRIVER("... pstate : %d\n", nouveau_pstate); > + DRM_DEBUG_DRIVER("... staging_tiling: %d\n", nouveau_staging_tiling); > } > > static const struct dev_pm_ops nouveau_pm_ops = { > diff --git a/drm/nouveau/nouveau_gem.c b/drm/nouveau/nouveau_gem.c > index 0e690bf19fc9..0e69449798aa 100644 > --- a/drm/nouv...

...ong > @@ -1029,6 +1034,7 @@ static void nouveau_display_options(void) > DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm); > DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf); > DRM_DEBUG_DRIVER("... pstate : %d\n", nouveau_pstate); > + DRM_DEBUG_DRIVER("... staging_tiling: %d\n", nouveau_staging_tiling); > } > > static const struct dev_pm_ops nouveau_pm_ops = { > diff --git a/drm/nouveau/nouveau_gem.c b/drm/nouveau/nouveau_gem.c > index 0e690bf19fc9..0e69449798aa 100644 > --- a/drm/nouv...

...riv); > +} > + > +#define GK20A_CLK_GPC_MDIV 1000 > + > +static struct nouveau_clocks > +gk20a_domains[] = { > + { nv_clk_src_crystal, 0xff }, > + { nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV }, > + { nv_clk_src_max } > +}; > + > +static struct nouveau_pstate > +gk20a_pstates[] = { > + { > + .base = { > + .domain[nv_clk_src_gpc] = 72000, > + }, > + }, > + { > + .base = { > + .domain[nv_clk_src_gpc] = 108000, > + }, > + }, > + { > + .base = { > + .domain[nv_clk_src_gpc] = 180000, > + }, > + }...