search for: nouveau_mm_init

...nouveau_object *parent, struct nouveau_object *engine, /* if all controllers have the same amount attached, there's no holes */ if (uniform) { offset = rsvd_head; - length = (ram->size >> 12) - rsvd_head - rsvd_tail; + length = (ram->size >> 12) - rsvd_head; ret = nouveau_mm_init(&pfb->vram, offset, length, 1); } else { /* otherwise, address lowest common amount from 0GiB */ @@ -167,7 +166,7 @@ nvc0_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, /* and the rest starting from (8GiB + common_size) */ offset = (0x0200000000ULL >...

...loc(vm->lpde - vm->fpde + 1, sizeof(*vm->pgt), GFP_KERNEL); + vm->pgt = vzalloc((vm->lpde - vm->fpde + 1) * sizeof(*vm->pgt)); if (!vm->pgt) { kfree(vm); return -ENOMEM; @@ -371,7 +371,7 @@ nouveau_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length, ret = nouveau_mm_init(&vm->mm, mm_offset >> 12, mm_length >> 12, block >> 12); if (ret) { - kfree(vm->pgt); + vfree(vm->pgt); kfree(vm); return ret; } @@ -446,7 +446,7 @@ nouveau_vm_del(struct nouveau_vm *vm) } nouveau_mm_fini(&vm->mm); - kfree(vm->pgt...

...-1; > if (ret) { > priv->num_tags = 0; > } else { Seems like you could just avoid a lot of this and just start the function out with if (!pfb->ram) { priv->num_tags = 0; (is that even necessary? the object is probably kzalloc'd) ret = nouveau_mm_init(&priv->tags, 0, 0, 1); return ret; } That's essentially what happens, no? Perhaps you could go a step further and teach the base code about uninitialized tags mm, but that may not be worth it. -ilia

.../ 4; if (priv->num_tags > (1 << 17)) @@ -152,7 +149,7 @@ nvc0_ltcg_init_tag_ram(struct nouveau_fb *pfb, struct nvc0_ltcg_priv *priv) tag_base += tag_align - 1; ret = do_div(tag_base, tag_align); - nv_wr32(priv, 0x17e8d4, tag_base); + priv->tag_base = tag_base; } ret = nouveau_mm_init(&priv->tags, 0, priv->num_tags, 1); @@ -182,8 +179,6 @@ nvc0_ltcg_ctor(struct nouveau_object *parent, struct nouveau_object *engine, } priv->subp_nr = nv_rd32(priv, 0x17e8dc) >> 28; - nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */ - ret = nv...

On Wed, Dec 10, 2014 at 5:53 PM, Pierre Moreau <pierre.morrow at free.fr> wrote: > (This is a v3 of patch "drm/nouveau/fb/nv50: Add PFB writes") > > This fix a GPU lockup on 9400M (NVAC) when using acceleration, see > https://bugs.freedesktop.org/show_bug.cgi?id=27501 > > v2: > - Move code to subdev/fb/nv50.c as suggested by Roy Spliet; > - Remove arbitrary

..., 1, size, size, max(align, (u32)1), &gpuobj->node); if (ret) - return ret; + goto err; gpuobj->addr += gpuobj->node->offset; } @@ -121,7 +121,7 @@ nouveau_gpuobj_create_(struct nouveau_object *parent, if (gpuobj->flags & NVOBJ_FLAG_HEAP) { ret = nouveau_mm_init(&gpuobj->heap, 0, gpuobj->size, 1); if (ret) - return ret; + goto err; } if (flags & NVOBJ_FLAG_ZERO_ALLOC) { @@ -130,6 +130,9 @@ nouveau_gpuobj_create_(struct nouveau_object *parent, } return ret; +err: + nouveau_gpuobj_destroy(gpuobj); + return ret; } struct n...

...t;tag_ram); if (ret) { priv->num_tags = 0; @@ -152,7 +149,7 @@ nvc0_ltcg_init_tag_ram(struct nouveau_fb *pfb, struct nvc0_ltcg_priv *priv) tag_base += tag_align - 1; ret = do_div(tag_base, tag_align); - nv_wr32(priv, 0x17e8d4, tag_base); + priv->tag_base = tag_base; } ret = nouveau_mm_init(&priv->tags, 0, priv->num_tags, 1); @@ -182,8 +179,6 @@ nvc0_ltcg_ctor(struct nouveau_object *parent, struct nouveau_object *engine, } priv->subp_nr = nv_rd32(priv, 0x17e8dc) >> 28; - nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */ - ret = nv...

...+ 1, sizeof(*vm->pgt), GFP_KERNEL); > + vm->pgt = vzalloc((vm->lpde - vm->fpde + 1) * sizeof(*vm->pgt)); > if (!vm->pgt) { > kfree(vm); > return -ENOMEM; > @@ -371,7 +371,7 @@ nouveau_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length, > ret = nouveau_mm_init(&vm->mm, mm_offset >> 12, mm_length >> 12, > block >> 12); > if (ret) { > - kfree(vm->pgt); > + vfree(vm->pgt); > kfree(vm); > return ret; > } > @@ -446,7 +446,7 @@ nouveau_vm_del(struct nouveau_vm *vm) > } > &gt...

.../ 4; if (priv->num_tags > (1 << 17)) @@ -152,7 +149,7 @@ nvc0_ltcg_init_tag_ram(struct nouveau_fb *pfb, struct nvc0_ltcg_priv *priv) tag_base += tag_align - 1; ret = do_div(tag_base, tag_align); - nv_wr32(priv, 0x17e8d4, tag_base); + priv->tag_base = tag_base; } ret = nouveau_mm_init(&priv->tags, 0, priv->num_tags, 1); @@ -182,8 +179,6 @@ nvc0_ltcg_ctor(struct nouveau_object *parent, struct nouveau_object *engine, } priv->subp_nr = nv_rd32(priv, 0x17e8dc) >> 28; - nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */ - ret = nv...

...uct nouveau_fb *pfb, struct nvc0_ltcg_priv *priv) > tag_base += tag_align - 1; > ret = do_div(tag_base, tag_align); > > - nv_wr32(priv, 0x17e8d4, tag_base); > + priv->tag_base = tag_base; > } > ret = nouveau_mm_init(&priv->tags, 0, priv->num_tags, 1); > > @@ -182,8 +179,6 @@ nvc0_ltcg_ctor(struct nouveau_object *parent, struct nouveau_object *engine, > } > priv->subp_nr = nv_rd32(priv, 0x17e8dc) >> 28; > > - nv_mask(priv, 0x17e820, 0x00100000, 0x000000...

Here's a quick-but-I-guess-tidy-fix for faulty behaviour someone reported in NVAF. I'm just not sure if the check for nvaa/nvac should still be in nv50_pm_clocks_pre... I believe this is wrong as they can reclock perfectly well (except the non-existing memory). Anyone has a definite answer to that?

.../* Use a fixed size of 64MB for now */ > + ram->size = 0x4000000; > + ram->stolen = (u64)0x00000000; > + vram = dma_alloc_coherent(nv_device_base(nv_device(parent)), ram->size, > + &dma_handle, GFP_KERNEL); > + if (!vram) > + return -ENOMEM; > + > + ret = nouveau_mm_init(&pfb->vram, dma_handle >> 12, ram->size >> 12, 1); > + if (ret) > + return ret; > + > + ram->get = nvc0_ram_get; > + ram->put = nvc0_ram_put; > + return 0; > +} > + > +struct nouveau_oclass > +nvea_ram_oclass = { > + .ofuncs = &(stru...

...+ ram->type = NV_MEM_TYPE_STOLEN; + /* Use a fixed size of 64MB for now */ + ram->size = 0x4000000; + ram->stolen = (u64)0x00000000; + vram = dma_alloc_coherent(nv_device_base(nv_device(parent)), ram->size, + &dma_handle, GFP_KERNEL); + if (!vram) + return -ENOMEM; + + ret = nouveau_mm_init(&pfb->vram, dma_handle >> 12, ram->size >> 12, 1); + if (ret) + return ret; + + ram->get = nvc0_ram_get; + ram->put = nvc0_ram_put; + return 0; +} + +struct nouveau_oclass +nvea_ram_oclass = { + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvea_ram_ctor, + .dtor...

...; + ram->stolen = (u64)0x00000000; >> + vram = dma_alloc_coherent(nv_device_base(nv_device(parent)), ram->size, >> + &dma_handle, GFP_KERNEL); >> + if (!vram) >> + return -ENOMEM; >> + >> + ret = nouveau_mm_init(&pfb->vram, dma_handle >> 12, ram->size >> 12, 1); >> + if (ret) >> + return ret; >> + >> + ram->get = nvc0_ram_get; >> + ram->put = nvc0_ram_put; >> + return 0; >> +} >> + >> +struct nouve...

...0x00000000; > >> + vram = dma_alloc_coherent(nv_device_base(nv_device(parent)), ram->size, > >> + &dma_handle, GFP_KERNEL); > >> + if (!vram) > >> + return -ENOMEM; > >> + > >> + ret = nouveau_mm_init(&pfb->vram, dma_handle >> 12, ram->size >> 12, 1); > >> + if (ret) > >> + return ret; > >> + > >> + ram->get = nvc0_ram_get; > >> + ram->put = nvc0_ram_put; > >> + return 0; > >> +...

...~align_mask; if (s > e || e - s < min) diff --git a/drivers/gpu/drm/nouveau/nouveau_mm.h b/drivers/gpu/drm/nouveau/nouveau_mm.h index 57a600c..d6e8f6a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_mm.h +++ b/drivers/gpu/drm/nouveau/nouveau_mm.h @@ -48,20 +48,20 @@ struct nouveau_mm { int nouveau_mm_init(struct nouveau_mm *, u32 offset, u32 length, u32 block); int nouveau_mm_fini(struct nouveau_mm *); int nouveau_mm_pre(struct nouveau_mm *); -int nouveau_mm_get(struct nouveau_mm *, int type, u32 size, u32 size_nc, - u32 align, struct nouveau_mm_node **); +int nouveau_mm_get(struct nouvea...

...ize, tag_size, 1, + &priv->tag_ram); + if (ret) { + priv->num_tags = 0; + } else { + u64 tag_base = (priv->tag_ram->offset << 12) + tag_margin; + + tag_base += tag_align - 1; + tag_base /= tag_align; + + nv_wr32(priv, 0x17e8d4, tag_base); + } + ret = nouveau_mm_init(&priv->tags, 0, priv->num_tags, 1); + + return ret; +} + +static int nvc0_ltcg_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) { struct nvc0_ltcg_priv *priv; + st...

Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into nouveau_display.c and nv84_fence.c. Original cover letter: Patches 1-3 make the presence of a RAM device optional, and remove GK20A's dummy RAM driver we were using so far. On chips using shared memory, such a device can confuse the driver into moving objects where there is no need to, and can trick

Hello everyone, GK20A is the Kepler-based GPU used in the upcoming Tegra K1 chips. The following patches perform architectural changes to Nouveau that are necessary to support non-PCI GPUs and add initial support for GK20A. Although the support is still very basic and more user-space changes will be needed to make the full graphics stack run on top of it, we were able to successfully open