Displaying 3 results from an estimated 3 matches for "nouveau_graph_trapped_channel".
2008 Aug 01
1
NV86 (Quadro NVS 140M) errors in dmesg
...00.0: PCI INT A -> GSI 16 (level, low) ->
IRQ 16
[ 21.749432] nouveau 0000:01:00.0: setting latency timer to 64
[ 21.749528] [drm] Detected an NV50 generation card (0x086900a2)
[ 21.749530] [drm] Initialized nouveau 0.0.11
drm-2.3.0-1351-g4585787bd1a1d782b on minor 0
[ 22.586502] [drm:nouveau_graph_trapped_channel] *ERROR* AIII,
invalid/inactive channel id 128
[ 22.586509] [drm] PGRAPH_ERROR - nSource: PROTECTION_ERROR, nStatus:
[ 22.586513] [drm] PGRAPH_ERROR - Ch -1/0 Class 0x0000 Mthd 0x0000
Data 0x00000000:0x00000000
[ 22.586521] [drm] Allocating FIFO number 1
[ 22.593281] [drm] nouveau_fifo_allo...
2010 Mar 01
0
[PATCH 2/2 V2] drm/nv50: Improve PGRAPH interrupt handling.
...ot;);
+ }
+
+ /* Known to be triggered by screwed up NOTIFY and COND... */
+ if (ustatus & 0x00000001) {
+ nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_DISPATCH_FAULT");
+ nv_wr32(dev, 0x400500, 0);
+ if (nv_rd32(dev, 0x400808) & 0x80000000) {
+ if (display) {
+ if (nouveau_graph_trapped_channel(dev, &trap.channel))
+ trap.channel = -1;
+ trap.class = nv_rd32(dev, 0x400814);
+ trap.mthd = nv_rd32(dev, 0x400808) & 0x1ffc;
+ trap.subc = (nv_rd32(dev, 0x400808) >> 16) & 0x7;
+ trap.data = nv_rd32(dev, 0x40080c);
+ trap.data2 = nv_rd32(dev, 0x400810);...
2010 Feb 28
1
[PATCH 1/2] drm/nv50: Make ctxprog wait until interrupt handler is done.
This will fix races between generated ctxprogs and interrupt handler.
Signed-off-by: Marcin Ko?cielnicki <koriakin at 0x04.net>
---
drivers/gpu/drm/nouveau/nv50_grctx.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nv50_grctx.c b/drivers/gpu/drm/nouveau/nv50_grctx.c
index d105fcd..9f909ab 100644
---