search for: nouveau_gpuobj_channel_init

...l_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret, INIT_LIST_HEAD(&chan->nvsw.vbl_wait); INIT_LIST_HEAD(&chan->nvsw.flip); INIT_LIST_HEAD(&chan->fence.pending); + spin_lock_init(&chan->fence.lock); /* setup channel's memory and vm */ ret = nouveau_gpuobj_channel_init(chan, vram_handle, gart_handle); diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c index c499591..614e37a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fence.c +++ b/drivers/gpu/drm/nouveau/nouveau_fence.c @@ -568,8 +568,6 @@ nouveau_fence_channel_init(st...

...u/drm/nouveau/nouveau_object.c @@ -33,6 +33,7 @@ #include "drmP.h" #include "drm.h" #include "nouveau_drv.h" +#include "nouveau_dma.h" #include "nouveau_drm.h" /* NVidia uses context objects to drive drawing operations. @@ -1099,6 +1100,41 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan, return ret; } + /* Two objects for kernel consumption, on nv50 they allow direct access + * to vram. This is needed because we don't know the tiling layout. + */ + vram = NULL; + ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, + 0, nouveau_me...

...[drm] Allocating FIFO number 0 Aug 6 21:11:46 localhost [drm:nouveau_notifier_init_channel] Allocating notifier block in 272 Aug 6 21:11:46 localhost [drm:drm_addmap_core] offset = 0x00000000, size = 0x00001000, type = 4 Aug 6 21:11:46 localhost [drm] allocated 0x0 Aug 6 21:11:46 localhost [drm:nouveau_gpuobj_channel_init] ch0 vram=0x8003d001 tt=0x8003d002 Aug 6 21:11:46 localhost [drm:nouveau_gpuobj_ref_add] ch-1 h=0x00000000 gpuobj=ffff81003a5a19c0 Aug 6 21:11:46 localhost [drm:nouveau_gpuobj_dma_new] ch0 class=0x003d offset=0x0 size=0x7f00000 Aug 6 21:11:46 localhost [drm:nouveau_gpuobj_dma_new] access=0 targe...