search for: nouveau_gddr5_calc

...ss nva3_ram_oclass; > extern struct nouveau_oclass nvaa_ram_oclass; > extern struct nouveau_oclass nvc0_ram_oclass; > extern struct nouveau_oclass nve0_ram_oclass; > +extern struct nouveau_oclass nvea_ram_oclass; > > int nouveau_sddr3_calc(struct nouveau_ram *ram); > int nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts); > diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvea.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvea.c > new file mode 100644 > index 0000000..3038e08 > --- /dev/null > +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvea.c > @@ -0,...

...rm/nouveau/core/subdev/fb/priv.h @@ -35,6 +35,7 @@ extern struct nouveau_oclass nve0_ram_oclass; extern struct nouveau_oclass gk20a_ram_oclass; extern struct nouveau_oclass gm107_ram_oclass; +int nouveau_sddr2_calc(struct nouveau_ram *ram); int nouveau_sddr3_calc(struct nouveau_ram *ram); int nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts); diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/sddr2.c b/drivers/gpu/drm/nouveau/core/subdev/fb/sddr2.c new file mode 100644 index 0000000..b5b0432 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/sddr2.c @@ -0,0 +1,96 @@ +/* + * Copyright 2014...

Sometimes boot scripts leave the "DLL reset" bit on, but it shouldn't be set on every MR write. V2 addresses this by forcing DLL reset off in MR generation

...eau/core/subdev/fb/priv.h +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h @@ -37,6 +37,7 @@ extern struct nouveau_oclass gm107_ram_oclass; int nouveau_sddr2_calc(struct nouveau_ram *ram); int nouveau_sddr3_calc(struct nouveau_ram *ram); +int nouveau_gddr3_calc(struct nouveau_ram *ram); int nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts); #define nouveau_fb_create(p,e,c,d) \ -- 1.9.3

...+32,7 @@ extern struct nouveau_oclass nva3_ram_oclass; extern struct nouveau_oclass nvaa_ram_oclass; extern struct nouveau_oclass nvc0_ram_oclass; extern struct nouveau_oclass nve0_ram_oclass; +extern struct nouveau_oclass nvea_ram_oclass; int nouveau_sddr3_calc(struct nouveau_ram *ram); int nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts); diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvea.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvea.c new file mode 100644 index 0000000..3038e08 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvea.c @@ -0,0 +1,67 @@ +/* + * Copyright (...

...t; extern struct nouveau_oclass nvaa_ram_oclass; >> extern struct nouveau_oclass nvc0_ram_oclass; >> extern struct nouveau_oclass nve0_ram_oclass; >> +extern struct nouveau_oclass nvea_ram_oclass; >> >> int nouveau_sddr3_calc(struct nouveau_ram *ram); >> int nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts); >> diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvea.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvea.c >> new file mode 100644 >> index 0000000..3038e08 >> --- /dev/null >> +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/r...

...ss nvaa_ram_oclass; > >> extern struct nouveau_oclass nvc0_ram_oclass; > >> extern struct nouveau_oclass nve0_ram_oclass; > >> +extern struct nouveau_oclass nvea_ram_oclass; > >> > >> int nouveau_sddr3_calc(struct nouveau_ram *ram); > >> int nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts); > >> diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvea.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvea.c > >> new file mode 100644 > >> index 0000000..3038e08 > >> --- /dev/null > >> +++ b/drivers/gpu/drm...

Patch 1 and 2 implement wait-for-vblank, required to remove flicker when reclocking memory Patch 3 and 4 allow me to do things between waiting for VBLANK and disabling FB, like pause PFIFO and wait for the engines to idle. This minimises the time PFIFO is paused, thus maximises performance. The rest of the patches speak for themselves. As the actual memory reclocking script is still somewhat prone

Hello everyone, GK20A is the Kepler-based GPU used in the upcoming Tegra K1 chips. The following patches perform architectural changes to Nouveau that are necessary to support non-PCI GPUs and add initial support for GK20A. Although the support is still very basic and more user-space changes will be needed to make the full graphics stack run on top of it, we were able to successfully open

Following a series of patches that implement memory reclocking for NVA3/5/8 with DDR2, DDR3 and GDDR3 on board. I tested these patches on 6 different graphics cards, but I expect reclocking now to work on many more. Testers can pick up these patches and test it by enabling pstate (nouveau.pstate=1). They should then be able to change clocks by writing to /sys/class/drm/card0/device/pstate. Correct

Hi everyone, Here is the second batch of patches to add GK20A support to Nouveau. This time we are adding the actual chip support, and this series brings the driver to a point where a slightly-tweaked Mesa successfully runs shaders and renders triangles on GBM! Many thanks to Thierry Reding and the people on the #nouveau IRC channel for their help without which we would not have reached this