search for: nouveau_dma_wait

A cleanup of nouveau_dma_wait(): extract a sub-function and eliminate two variables to improve readability. No functional changes. Signed-off-by: Pekka Paalanen <pq at iki.fi> --- drivers/gpu/drm/nouveau/nouveau_dma.c | 72 ++++++++++++++++++--------------- 1 files changed, 39 insertions(+), 33 deletions(-) diff --g...

...>bo.mem.size) { + /* meaningless to dma_wait() except to know whether the + * GPU has stalled or not + */ + *get = val; return false; + } *get = (val - chan->pushbuf_base) >> 2; return true; @@ -123,54 +128,79 @@ READ_GET(struct nouveau_channel *chan, uint32_t *get) int nouveau_dma_wait(struct nouveau_channel *chan, int size) { - const int us_timeout = 100000; - uint32_t get; - int ret = -EBUSY, i; + uint32_t get, prev_get = 0, cnt = 0; + bool get_valid; + + while (chan->dma.free < size) { + /* reset counter as long as GET is still advancing, this is + * to avoid misdete...

...USH)) { NV_ERROR(drm, "pushbuf push count exceeds limit: %d max %d\n", req->nr_push, NOUVEAU_GEM_MAX_PUSH); return nouveau_abi16_put(abi16, -EINVAL); @@ -718,7 +718,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data, } if (chan->dma.ib_max) { - ret = nouveau_dma_wait(chan, req->nr_push + 1, 16); + ret = nouveau_dma_wait(chan, req->nr_push, 16); if (ret) { NV_ERROR(drm, "nv50cal_space: %d\n", ret); goto out; -- 1.7.8.6

Before this patch they were being reset to zero on every context switch instead of leaving the saved value, causing some context switching weirdness (the most serious symptom was the memory manager corrupting the BOs it migrated because of a malfunctioning M2MF). Signed-off-by: Francisco Jerez <currojerez at riseup.net> --- drivers/gpu/drm/nouveau/nv10_graph.c | 3 ++- 1 files changed,

...t;c014c44b>] warn_slowpath_fmt+0x2b/0x30 May 14 19:17:28 max-desktop kernel: [ 3.743594] [<c0356215>] bad_io_access+0x45/0x50 May 14 19:17:28 max-desktop kernel: [ 3.743607] [<c0356582>] ioread32+0x22/0x40 May 14 19:17:28 max-desktop kernel: [ 3.743667] [<d8a286c8>] nouveau_dma_wait+0x38/0x1b0 [nouveau] May 14 19:17:28 max-desktop kernel: [ 3.743715] [<d8a2a4ec>] nouveau_fence_emit+0x12c/0x170 [nouveau] May 14 19:17:28 max-desktop kernel: [ 3.743763] [<d8a2a5b0>] nouveau_fence_new+0x80/0xe0 [nouveau] May 14 19:17:28 max-desktop kernel: [ 3.743778] [<...

http://bugs.freedesktop.org/show_bug.cgi?id=17377 Summary: NV50 failure on MacBook Pro. Product: xorg Version: git Platform: Other OS/Version: All Status: NEW Severity: normal Priority: medium Component: Driver/nouveau AssignedTo: nouveau at lists.freedesktop.org ReportedBy: dwmw2 at

...->dma.ib_max; diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h index 035a709c7be1..1744d95b233e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h @@ -31,7 +31,8 @@ #include "nouveau_chan.h" int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); -void nv50_dma_push(struct nouveau_channel *, u64 addr, int length); +void nv50_dma_push(struct nouveau_channel *, u64 addr, u32 length, + bool no_prefetch); /* * There's a hw race condition where you can't jump to your PUT offset, @@...

...s/gpu/drm/nouveau/nouveau_dma.h > b/drivers/gpu/drm/nouveau/nouveau_dma.h > index 035a709c7be1..fb471c357336 100644 > --- a/drivers/gpu/drm/nouveau/nouveau_dma.h > +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h > @@ -31,7 +31,8 @@ > #include "nouveau_chan.h" > > int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); > -void nv50_dma_push(struct nouveau_channel *, u64 addr, int length); > +void nv50_dma_push(struct nouveau_channel *, u64 addr, u32 length, > + bool prefetch); > > /* > * There's a hw race condition where you...

...->dma.ib_max; diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h index 035a709c7be1..fb471c357336 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h @@ -31,7 +31,8 @@ #include "nouveau_chan.h" int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); -void nv50_dma_push(struct nouveau_channel *, u64 addr, int length); +void nv50_dma_push(struct nouveau_channel *, u64 addr, u32 length, + bool prefetch); /* * There's a hw race condition where you can't jump to your PUT offset, @@ -4...

...nouveau_acpi.o obj-$(CONFIG_DRM_NOUVEAU)+= nouveau.o diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index d72bb1f..fad07cc 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -1097,7 +1097,7 @@ extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); /* nouveau_acpi.c */ #define ROM_BIOS_PAGE 4096 -#if defined(CONFIG_ACPI) +#if defined(CONFIG_DRM_NOUVEAU_ACPI) void nouveau_register_dsm_handler(void); void nouveau_unregister_dsm_handler(void); void nouveau_switcheroo_optimus_dsm(void); -- 1...

...nouveau_acpi.o obj-$(CONFIG_DRM_NOUVEAU)+= nouveau.o diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index b793697..1fb7894 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -1070,7 +1070,7 @@ extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); /* nouveau_acpi.c */ #define ROM_BIOS_PAGE 4096 -#if defined(CONFIG_ACPI) +#if defined(CONFIG_DRM_NOUVEAU_ACPI) void nouveau_register_dsm_handler(void); void nouveau_unregister_dsm_handler(void); int nouveau_acpi_get_bios_chunk(uint8_t *bios, i...

Not holding the mutex potentially causes corruption of the kernel channel when page flipping. Cc: stable at vger.kernel.org #3.13 Signed-off-by: Maarten Lankhorst <maarten.lankhorst at canonical.com> --- diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index 29c3efdfc7dd..76e3cf025c10 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c

http://bugs.freedesktop.org/show_bug.cgi?id=14284 Summary: frequent DMA queue hangs on NV34 on powerpc Product: xorg Version: git Platform: PowerPC OS/Version: All Status: NEW Severity: normal Priority: medium Component: Driver/nouveau AssignedTo: nouveau at lists.freedesktop.org

...uint64_t ramin_size; } susres; + struct backlight_device *backlight; }; #define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \ @@ -468,6 +469,10 @@ extern int nouveau_dma_channel_init(struct drm_device *); extern void nouveau_dma_channel_takedown(struct drm_device *); extern int nouveau_dma_wait(struct drm_device *, int size); +/* nouveau_backlight.c */ +extern int nouveau_backlight_init(struct drm_device *); +extern void nouveau_backlight_exit(struct drm_device *); + /* nv04_fb.c */ extern int nv04_fb_init(struct drm_device *); extern void nv04_fb_takedown(struct drm_device *); diff...

From: Thierry Reding <treding at nvidia.com> Hi, This series implements a new IOCTL to submit push buffers that can optionally return a sync FD or sync object to userspace. This is useful in cases where userspace wants to synchronize operations between the GPU and another driver (such as KMS for display). Among other things this allows extensions such as eglDupNativeFenceFDANDROID to be

Reduces object size ~4kb Joe Perches (2): drm/nouveau: Add new logging function nv_cli_printk drm/nouveau: Convert NV_PRINTK macros and uses to new nv_cli_<level> macros drivers/gpu/drm/nouveau/nouveau_abi16.c | 2 +- drivers/gpu/drm/nouveau/nouveau_chan.c | 12 +++---- drivers/gpu/drm/nouveau/nouveau_drm.c | 21 +++++++++++ drivers/gpu/drm/nouveau/nouveau_drv.h | 44

From: Maarten Lankhorst <maarten.lankhorst at canonical.com> Commit de7b7d59d54852c introduced tiled GART, but a linear copy is still performed. This may result in errors on eviction, fix it by checking tiling from memtype. Signed-off-by: Maarten Lankhorst <maarten.lankhorst at canonical.com> Cc: stable at vger.kernel.org #3.10+ --- drivers/gpu/drm/nouveau/nouveau_bo.c | 33

Hi guys, I'd like to start a new thread about explicit fence synchronization. This time with a Nouveau twist. :-) First, let me define what I understand by implicit/explicit sync: Implicit synchronization * Fences are attached to buffers * Kernel manages fences automatically based on buffer read/write access Explicit synchronization * Fences are passed around independently * Kernel takes