search for: nouveau_dma_skip

...ET(struct nouveau_channel *chan, uint32_t *get) return true; } +static int +dma_wait_ring_wrap(struct nouveau_channel *chan, int size, uint32_t get, + int *timeout) +{ + /* Emit jump to the start of the ring buffer. */ + OUT_RING(chan, 0x20000000 | chan->pushbuf_base); + + if (get <= NOUVEAU_DMA_SKIPS) { + /* corner case - will be idle */ + if (chan->dma.put <= NOUVEAU_DMA_SKIPS) + WRITE_PUT(NOUVEAU_DMA_SKIPS + 1); + + for (; *timeout; (*timeout)--) { + if (READ_GET(chan, &get) && get > NOUVEAU_DMA_SKIPS) + break; + + DRM_UDELAY(1); + } + + if (*timeout == 0)...

...{ DRM_UDELAY(1); - continue; + if (cnt > 10000) + return -EBUSY; } - if (chan->dma.put >= get) { - chan->dma.free = chan->dma.max - chan->dma.cur; - - if (chan->dma.free < size) { - OUT_RING(chan, 0x20000000|chan->pushbuf_base); - if (get <= NOUVEAU_DMA_SKIPS) { - /*corner case - will be idle*/ - if (chan->dma.put <= NOUVEAU_DMA_SKIPS) - WRITE_PUT(NOUVEAU_DMA_SKIPS + 1); - - for (; i < us_timeout; i++) { - if (READ_GET(chan, &get) && - get > NOUVEAU_DMA_SKIPS) - break; - - DRM_UDELAY(1);...

Before this patch they were being reset to zero on every context switch instead of leaving the saved value, causing some context switching weirdness (the most serious symptom was the memory manager corrupting the BOs it migrated because of a malfunctioning M2MF). Signed-off-by: Francisco Jerez <currojerez at riseup.net> --- drivers/gpu/drm/nouveau/nv10_graph.c | 3 ++- 1 files changed,

If you're especially unlucky BOs would move around and their kmaps would end up pointing to something else in GART, then ioctl_pushbuf() would use the kmaps again corrupting textures or other pushbufs (the most noticeable symptom was a PFIFO_DMA_PUSHER from time to time). Signed-off-by: Francisco Jerez <currojerez at riseup.net> --- drivers/gpu/drm/nouveau/nouveau_gem.c | 2 ++ 1

...7,11 +77,9 @@ return ret; /* Map M2MF notifier object - fbcon. */ - if (drm_core_check_feature(dev, DRIVER_MODESET)) { - ret = nouveau_bo_map(chan->notifier_bo); - if (ret) - return ret; - } + ret = nouveau_bo_map(chan->notifier_bo); + if (ret) + return ret; /* Insert NOPS for NOUVEAU_DMA_SKIPS */ ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS); diff -Naur a/drivers/gpu/drm/nouveau/nouveau_drv.c b/drivers/gpu/drm/nouveau/nouveau_drv.c --- a/drivers/gpu/drm/nouveau/nouveau_drv.c 2010-01-18 12:42:14.396872703 +0100 +++ b/drivers/gpu/drm/nouveau/nouveau_drv.c 2010-01-18 13:00:57.044879755 +0100...

...addr, int length); +void nv50_dma_push(struct nouveau_channel *, u64 addr, u32 length, + bool no_prefetch); /* * There's a hw race condition where you can't jump to your PUT offset, @@ -45,6 +46,9 @@ void nv50_dma_push(struct nouveau_channel *, u64 addr, int length); */ #define NOUVEAU_DMA_SKIPS (128 / 4) +/* Maximum push buffer size. */ +#define NV50_DMA_PUSH_MAX_LENGTH 0x7fffff + /* Object handles - for stuff that's doesn't use handle == oclass. */ enum { NvDmaFB = 0x80000002, @@ -89,7 +93,7 @@ FIRE_RING(struct nouveau_channel *chan) if (chan->dma.ib_max) { nv50...

...ouveau_channel *, u64 addr, u32 length, > + bool prefetch); > > /* > * There's a hw race condition where you can't jump to your PUT offset, > @@ -45,6 +46,9 @@ void nv50_dma_push(struct nouveau_channel *, u64 addr, > int length); > */ > #define NOUVEAU_DMA_SKIPS (128 / 4) > > +/* Maximum push buffer size. */ > +#define NV50_DMA_PUSH_MAX_LENGTH 0x7fffff > + > /* Object handles - for stuff that's doesn't use handle == oclass. */ > enum { > NvDmaFB = 0x80000002, > @@ -89,7 +93,7 @@ FIRE_RING(struct nouveau_ch...

Introduce accessors for TTM buffer object memory that has been mapped into the kernel virtual address space or as IO memory. IO memory needs to be accessed via special accessor functions, not by dereferencing the iomem cookie. The wrappers hide the details of 32-bit access and honour the TTM map type. nv04_crtc_cursor_set() is changed to use the new wrappers. 'cursor' is received from

...u64 addr, int length); +void nv50_dma_push(struct nouveau_channel *, u64 addr, u32 length, + bool prefetch); /* * There's a hw race condition where you can't jump to your PUT offset, @@ -45,6 +46,9 @@ void nv50_dma_push(struct nouveau_channel *, u64 addr, int length); */ #define NOUVEAU_DMA_SKIPS (128 / 4) +/* Maximum push buffer size. */ +#define NV50_DMA_PUSH_MAX_LENGTH 0x7fffff + /* Object handles - for stuff that's doesn't use handle == oclass. */ enum { NvDmaFB = 0x80000002, @@ -89,7 +93,7 @@ FIRE_RING(struct nouveau_channel *chan) if (chan->dma.ib_max) { nv50...

From: Thierry Reding <treding at nvidia.com> Hi, This series implements a new IOCTL to submit push buffers that can optionally return a sync FD or sync object to userspace. This is useful in cases where userspace wants to synchronize operations between the GPU and another driver (such as KMS for display). Among other things this allows extensions such as eglDupNativeFenceFDANDROID to be

Revised patch set v2. [PATCH 1/8] drm/nouveau: bo read/write wrappers for nv04_crtc.c [PATCH 2/8] drm/nouveau: use bo accessors for push buffers [PATCH 3/8] drm/nouveau: OUT_RINGp - optimize OUT_RING loops [PATCH 4/8] drm/nv50: proper notifier_bo access in nv50_display_vblank_crtc_handler() [PATCH 5/8] drm/nouveau: access fbcon notifier via bo accessors [PATCH 6/8] drm/nouveau: screen_base and

Reduces object size ~4kb Joe Perches (2): drm/nouveau: Add new logging function nv_cli_printk drm/nouveau: Convert NV_PRINTK macros and uses to new nv_cli_<level> macros drivers/gpu/drm/nouveau/nouveau_abi16.c | 2 +- drivers/gpu/drm/nouveau/nouveau_chan.c | 12 +++---- drivers/gpu/drm/nouveau/nouveau_drm.c | 21 +++++++++++ drivers/gpu/drm/nouveau/nouveau_drv.h | 44