search for: nouveau_buffer_status_gpu_writ

...eau/nv50/nv50_state_validate.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c @@ -61,7 +61,7 @@ nv50_validate_fb(struct nv50_context *nv50) if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING) nv50->state.rt_serialize = TRUE; mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING; - mt->base.status &= NOUVEAU_BUFFER_STATUS_GPU_READING; + mt->base.status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING; /* only register for writing, otherwise we'd always serialize here */ BCTX_REFN(nv50->bufctx_3d, FB, &mt->base, WR); @@ -91,7 +9...

...else { align_free(tx->map - (tx->base.box.x & NOUVEAU_MIN_BUFFER_MAP_ALIGN_MASK)); @@ -572,11 +572,11 @@ nouveau_copy_buffer(struct nouveau_context *nv, src->bo, src->offset + srcx, src->domain, size); dst->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING; - nouveau_fence_ref(nv->screen->fence.current, &dst->fence); - nouveau_fence_ref(nv->screen->fence.current, &dst->fence_wr); + nouveau_fence_ref(nv->fence.current, &dst->fence); + nouveau_fence_ref(nv->fence.current, &dst->fence_...

Signed-off-by: Maarten Lankhorst <maarten.lankhorst at canonical.com> --- src/gallium/drivers/nouveau/nouveau_fence.c | 76 ++++++++++++------------- src/gallium/drivers/nouveau/nouveau_fence.h | 22 +++++-- src/gallium/drivers/nouveau/nouveau_screen.c | 9 +++ src/gallium/drivers/nouveau/nouveau_screen.h | 14 ++--- src/gallium/drivers/nouveau/nv30/nv30_context.c | 4 +-

...free(tx->map - > (tx->base.box.x & NOUVEAU_MIN_BUFFER_MAP_ALIGN_MASK)); > @@ -572,11 +572,11 @@ nouveau_copy_buffer(struct nouveau_context *nv, > src->bo, src->offset + srcx, src->domain, size); > > dst->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING; > - nouveau_fence_ref(nv->screen->fence.current, &dst->fence); > - nouveau_fence_ref(nv->screen->fence.current, &dst->fence_wr); > + nouveau_fence_ref(nv->fence.current, &dst->fence); > + nouveau_fence_ref(nv->fence.current,...

...pipe_h264_picture_desc *desc, > + struct nv84_video_buffer *dest) > +{ ... > + for (i = 0; i < 2; i++) { for (i = 0; i < dest->num_planes; i++) { > + struct nv50_miptree *mt = nv50_miptree(dest->resources[i]); > + mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING; > + } > + > + PUSH_KICK (push); > +} > + ... > +void > +nv84_decoder_vp_mpeg12_mb(struct nv84_decoder *dec, > + struct pipe_mpeg12_picture_desc *desc, > + const struct pipe_mpeg12_macroblock *macrob) > +{ ......

...+ struct nv84_video_buffer *dest) >> +{ > ... > >> + for (i = 0; i < 2; i++) { > for (i = 0; i < dest->num_planes; i++) { > >> + struct nv50_miptree *mt = nv50_miptree(dest->resources[i]); >> + mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING; >> + } >> + >> + PUSH_KICK (push); >> +} >> + > ... > >> +void >> +nv84_decoder_vp_mpeg12_mb(struct nv84_decoder *dec, >> + struct pipe_mpeg12_picture_desc *desc, >> + const struct...

...to. It will be copied + * back into VRAM on unmap. */ if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) buf->status &= NOUVEAU_BUFFER_STATUS_REALLOC_MASK; nouveau_transfer_staging(nv, tx, TRUE); } else { if (buf->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) { + /* The GPU is currently writing to this buffer. Copy its current + * contents to a staging area in the GART. This is necessary since + * not the whole area being mapped is being discarded. + */ if (buf->data) { a...

...84_video_buffer *dest) >>> +{ >> ... >> >>> + for (i = 0; i < 2; i++) { >> for (i = 0; i < dest->num_planes; i++) { >> >>> + struct nv50_miptree *mt = nv50_miptree(dest->resources[i]); >>> + mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING; >>> + } >>> + >>> + PUSH_KICK (push); >>> +} >>> + >> ... >> >>> +void >>> +nv84_decoder_vp_mpeg12_mb(struct nv84_decoder *dec, >>> + struct pipe_mpeg12_picture_desc *desc, >>&...

Signed-off-by: Maarten Lankhorst <maarten.lankhorst at canonical.com> --- src/gallium/drivers/nouveau/nouveau_fence.c | 76 ++++++++++++------------- src/gallium/drivers/nouveau/nouveau_fence.h | 22 +++++-- src/gallium/drivers/nouveau/nouveau_screen.c | 9 +++ src/gallium/drivers/nouveau/nouveau_screen.h | 14 ++--- src/gallium/drivers/nouveau/nv30/nv30_context.c | 4

...t;fence->offset); + PUSH_DATA (push, 1); + + /* Write to the semaphore location, intr */ + BEGIN_NV04(push, SUBC_VP(0x304), 1); + PUSH_DATA (push, 0x101); + + for (i = 0; i < 2; i++) { + struct nv50_miptree *mt = nv50_miptree(dest->resources[i]); + mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING; + } + + PUSH_KICK (push); +} + +static INLINE int16_t inverse_quantize(int16_t val, uint8_t quant, int mpeg1) { + /* This is wrong for non-intra mbs... but mpeg12_bitstream doesn't pass us + * the right data to do it right. Need to + sign() before the quant + * scale. */ + int...

...t;fence->offset); + PUSH_DATA (push, 1); + + /* Write to the semaphore location, intr */ + BEGIN_NV04(push, SUBC_VP(0x304), 1); + PUSH_DATA (push, 0x101); + + for (i = 0; i < 2; i++) { + struct nv50_miptree *mt = nv50_miptree(dest->resources[i]); + mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING; + } + + PUSH_KICK (push); +} + +static INLINE int16_t inverse_quantize(int16_t val, uint8_t quant, int mpeg1) { + int16_t ret = val * quant / 16; + if (mpeg1 && ret) { + if (ret > 0) + ret = (ret - 1) | 1; + else + ret = (ret + 1) | 1; + } + if (...

As it turns out, with the proprietary firmware, the VP3 and VP4 interfaces are identical. Furthermore, this is all already implemented for nvc0. So these patches (a) move the easily sharable bits of the nvc0 implementation into the nouveau directory, and then (b) implement the other parts in nv50. The non-shared parts are still largely copies, but there are some differences, not the least of which