search for: nouveau_bo_vma_find

...it(&nvbo->bo, false, false, false); nouveau_vm_unmap(vma); } diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.h b/drivers/gpu/drm/nouveau/nouveau_bo.h index dec51b1..61b8980 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.h +++ b/drivers/gpu/drm/nouveau/nouveau_bo.h @@ -84,6 +84,7 @@ nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, struct nouveau_vma *); void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); +void nouveau_bo_vma_del_reserved(struct nouveau_bo *, struct nouveau_vma *); /* TODO: sub...

...void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, bool no_wait_gpu); +void nouveau_bo_sync_for_device(struct nouveau_bo *nvbo); +void nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo); struct nouveau_vma * nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index c90c0dc0afe8..08829a720891 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c @@ -896,6 +896,7 @@ nouveau_gem_ioctl...

Second version of this patchset addressing Ben's comments and fixing a few extra things. This patchset proposes to introduce a "staging" module option to dynamically enable features (mostly ioctls) that are merged but may be refined before they are declared "stable". The second patch illustrates the use of this staging option with the SET_TILING ioctl, which can be used to

...bject(entry); + struct ttm_buffer_object *bo = &nvbo->bo; + + ttm_bo_reference(&nvbo->bo); + spin_unlock(&filp->table_lock); + + ret = ww_mutex_lock_interruptible(&nvbo->bo.resv->lock, NULL); + if (ret) { + ttm_bo_unref(&bo); + return ret; + } + + vma = nouveau_bo_vma_find(nvbo, cli->base.vm); + if (vma) + dump_single_bo(m, nvbo, id, vma); + else + WARN_ON(1); + ww_mutex_unlock(&nvbo->bo.resv->lock); + ttm_bo_unref(&bo); + + spin_lock(&filp->table_lock); + } + spin_unlock(&filp->table_lock); + return ret; +} + +static int +nouv...

...au_bo *, struct nouveau_fence *); > int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, > bool no_wait_gpu); > +void nouveau_bo_sync_for_device(struct nouveau_bo *nvbo); > +void nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo); > > struct nouveau_vma * > nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); > diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c > index c90c0dc0afe8..08829a720891 100644 > --- a/drivers/gpu/drm/nouveau/nouveau_gem.c > +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c > @@ -896,6 +8...

Another revision of this patchset critical for GK20A to operate. Previous attempts were exclusively using either TTM's regular page allocator or the DMA API one. Both have their advantages and drawbacks: the page allocator is fast but requires explicit synchronization on non-coherent architectures, whereas the DMA allocator always returns coherent memory, but is also slower, creates a

This patchset proposes to introduce a "staging" module option to dynamically enable features (mostly ioctls) that are merged but may be refined before they are declared "stable". The second patch illustrates the use of this staging option with the SET_TILING ioctl, which can be used to specify the tiling options of a PRIME-imported buffer. The staging parameter will allow us

For this v2 I have fixed the patches that are non-controversial (all Lucas' :)) and am resubmitting them in the hope that they will get merged. This will just leave the issue of Nouveau system-memory buffers mapping to be solved. This issue is quite complex, so let me summarize the situation and the data I have at hand. ARM caching is like a quantum world where Murphy's law constantly

It has been a couple of months since v4 - apologies for this. v4 has not received many comments, but this version addresses them and makes a new attempt at pushing the critical bit for GK20A and Nouveau on ARM in general. As a reminder, this series addresses the memory coherency issue that we are seeing on ARM platforms. Contrary to x86 which invalidates the PCI caches whenever a write is made by

...if (ret) > + goto out; > + > + nvbo->tile_mode = req->tile_mode; > + nvbo->tile_flags = req->tile_flags; > + > + nouveau_bo_update_tiling(drm, nvbo, nvbo->bo.mem.mm_node); > + > + /* remap over existing mapping with new tile parameters */ > + vma = nouveau_bo_vma_find(nvbo, cli->vm); > + if (vma) > + nvkm_vm_map(vma, nvbo->bo.mem.mm_node); > + > + ttm_bo_unreserve(&nvbo->bo); > + } > + > +out: > + drm_gem_object_unreference_unlocked(gem); > + return ret; > +} > + > int > nouveau_gem_new(struct drm_devic...

...if (ret) > + goto out; > + > + nvbo->tile_mode = req->tile_mode; > + nvbo->tile_flags = req->tile_flags; > + > + nouveau_bo_update_tiling(drm, nvbo, nvbo->bo.mem.mm_node); > + > + /* remap over existing mapping with new tile parameters */ > + vma = nouveau_bo_vma_find(nvbo, cli->vm); > + if (vma) > + nvkm_vm_map(vma, nvbo->bo.mem.mm_node); > + > + ttm_bo_unreserve(&nvbo->bo); > + } > + > +out: > + drm_gem_object_unreference_unlocked(gem); > + return ret; > +} > + > int > nouveau_gem_new(struct drm_device...

https://bugs.freedesktop.org/show_bug.cgi?id=92504 Bug ID: 92504 Summary: [NVA5] Corruption in Plasma 5 on resume after changing screen configuration Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: normal Priority: medium

Hi guys, I'd like to start a new thread about explicit fence synchronization. This time with a Nouveau twist. :-) First, let me define what I understand by implicit/explicit sync: Implicit synchronization * Fences are attached to buffers * Kernel manages fences automatically based on buffer read/write access Explicit synchronization * Fences are passed around independently * Kernel takes