search for: nouveau_bo_validate

...ingle_for_cpu(device->pdev, + ttm_dma->dma_address[i], PAGE_SIZE, + PCI_DMA_FROMDEVICE); + } else { + for (i = 0; i < ttm_dma->ttm.num_pages; i++) + dma_sync_single_for_cpu(nv_device_base(device), + ttm_dma->dma_address[i], PAGE_SIZE, + DMA_FROM_DEVICE); + } +} + int nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, bool no_wait_gpu) @@ -418,6 +472,8 @@ nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, if (!ttm) return ret; + nouveau_bo_sync_for_device(nvbo); + device = nouveau_dev(nouveau_bdev(ttm->bdev)->dev); nv_wr32(device,...

...+++ > 2 files changed, 9 insertions(+) > > diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c > index af20fba..f4a2eb9 100644 > --- a/drivers/gpu/drm/nouveau/nouveau_bo.c > +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c > @@ -411,6 +411,10 @@ nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, > { > int ret; > > + if (nvbo->bo.ttm && nvbo->bo.ttm->caching_state == tt_cached) You don't want to do it also for tt_wc ? > + ttm_dma_tt_cache_sync_for_device((struct ttm_dma_tt *)nvbo->bo.ttm, > + &a...

Another revision of this patchset critical for GK20A to operate. Previous attempts were exclusively using either TTM's regular page allocator or the DMA API one. Both have their advantages and drawbacks: the page allocator is fast but requires explicit synchronization on non-coherent architectures, whereas the DMA allocator always returns coherent memory, but is also slower, creates a

..., 59 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c > index b6dc85c614be..0886f47e5244 100644 > --- a/drivers/gpu/drm/nouveau/nouveau_bo.c > +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c > @@ -407,6 +407,8 @@ nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, > { > int ret; > > + nouveau_bo_sync_for_device(nvbo); > + > ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, > interruptible, no_wait_gpu); > if (ret) > @@ -487,6 +489,36 @@ nouveau_bo_invali...

It has been a couple of months since v4 - apologies for this. v4 has not received many comments, but this version addresses them and makes a new attempt at pushing the critical bit for GK20A and Nouveau on ARM in general. As a reminder, this series addresses the memory coherency issue that we are seeing on ARM platforms. Contrary to x86 which invalidates the PCI caches whenever a write is made by

...ts: > Warning: Type "ONE_LEVEL" has 1 levels, but <RALT> has 2 symbols > Ignoring extra symbols Errors from xkbcomp are not fatal to the X server SetClientVersion: 0 9 SetKbdSettings - type: 23658688 rate: 30 delay: 500 snumlk: 0 X: nouveau_bo.c:169: nouveau_bo_validate: Assertion `!r->bo->base.map' failed. gdb backtrace : Program received signal SIGABRT, Aborted. [Switching to Thread 47802344089392 (LWP 15759)] 0x00002b79d98ada55 in raise () from /lib64/libc.so.6 (gdb) bt #0 0x00002b79d98ada55 in raise () from /lib64/libc.so.6 #1 0x00002b79d98af1...

...ress[i], PAGE_SIZE, > + PCI_DMA_FROMDEVICE); > + } else { > + for (i = 0; i < ttm_dma->ttm.num_pages; i++) > + dma_sync_single_for_cpu(nv_device_base(device), > + ttm_dma->dma_address[i], PAGE_SIZE, > + DMA_FROM_DEVICE); > + } > +} > + > int > nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, > bool no_wait_gpu) > @@ -418,6 +472,8 @@ nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, > if (!ttm) > return ret; > > + nouveau_bo_sync_for_device(nvbo); > + > device = nouveau_dev(nouveau_bdev(t...

...ffa034745f>] nouveau_bo_move+0xb9/0x3cb [nouveau] [<ffffffffa01979e3>] ttm_bo_handle_move_mem+0x24e/0x6b0 [ttm] [<ffffffffa0198da4>] ttm_bo_move_buffer+0x157/0x164 [ttm] [<ffffffffa0198e51>] ttm_bo_validate+0xa0/0x129 [ttm] [<ffffffffa0347c80>] nouveau_bo_validate+0x1c/0x1e [nouveau] [<ffffffffa0347d52>] nouveau_ttm_fault_reserve_notify+0xd0/0xd7 [nouveau] [<ffffffffa019abad>] ttm_bo_vm_fault+0x69/0x394 [ttm] [<ffffffff8114eaed>] __do_fault+0x6e/0x496 [<ffffffff811515fb>] handle_pte_fault+0x84/0x861...

...ct nouveau_drm *drm = nouveau_bdev(bo->bdev); > + struct nouveau_bo *nvbo = nouveau_bo(bo); > + > + mutex_lock(&drm->ttm.io_reserve_mutex); > + list_del_init(&nvbo->io_reserve_lru); > + mutex_unlock(&drm->ttm.io_reserve_mutex); > +} > + > int > nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, > bool no_wait_gpu) > @@ -675,8 +697,6 @@ nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, > } > > man->func = &nouveau_vram_manager; > - man->io_reserve_fastpath = false; > - man...

For this v2 I have fixed the patches that are non-controversial (all Lucas' :)) and am resubmitting them in the hope that they will get merged. This will just leave the issue of Nouveau system-memory buffers mapping to be solved. This issue is quite complex, so let me summarize the situation and the data I have at hand. ARM caching is like a quantum world where Murphy's law constantly

...;] debug_dma_sync_single_for_device+0x7d/0x90 [ 37.496989] [<f7e22298>] ? ttm_bo_del_sub_from_lru+0x18/0x50 [ttm] [ 37.497006] [<c040b650>] ? text_poke_bp+0xd0/0xd0 [ 37.497144] [<f85ba340>] nouveau_bo_sync_for_device+0x80/0xc0 [nouveau] [ 37.497228] [<f85ba474>] nouveau_bo_validate+0x34/0x40 [nouveau] [ 37.497310] [<f85ba608>] nouveau_bo_pin+0x188/0x290 [nouveau] [ 37.497391] [<f85b8b60>] ? nv10_bo_put_tile_region+0x80/0x80 [nouveau] [ 37.497413] [<f85cd830>] nouveau_channel_prep+0x140/0x330 [nouveau] [ 37.497413] [<f85cda92>] nouveau_chann...

...uveau_bo_tile_layout(nvbo)) - return 0; - } - - /* make sure bo is in mappable vram */ - if (bo->mem.start + bo->mem.num_pages < mappable) - return 0; - - - nvbo->placement.fpfn = 0; - nvbo->placement.lpfn = mappable; - nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0); - return nouveau_bo_validate(nvbo, false, false); -} - -static int nouveau_ttm_tt_populate(struct ttm_tt *ttm) { struct ttm_dma_tt *ttm_dma = (void *)ttm; @@ -1524,7 +1496,6 @@ struct ttm_bo_driver nouveau_bo_driver = { .sync_obj_flush = nouveau_bo_fence_flush, .sync_obj_unref = nouveau_bo_fence_unref, .sync_obj_ref...

...nouveau_bdev(bo->bdev); > + struct nouveau_bo *nvbo = nouveau_bo(bo); > + > + mutex_lock(&drm->ttm.io_reserve_mutex); > + list_del_init(&nvbo->io_reserve_lru); > + mutex_unlock(&drm->ttm.io_reserve_mutex); > +} > + > int > nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, > bool no_wait_gpu) > @@ -675,8 +697,6 @@ nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, > } > > man->func = &nouveau_vram_manager; > -...

Hi guys, I've already send this out in September last year, but only got a response from Daniel. Could you guys please test this and tell me what you think about it? Basically I'm trying to remove all driver specific features from TTM which don't need to be inside the framework. Thanks, Christian.

...rve_lru(struct ttm_buffer_object *bo) +{ + struct nouveau_drm *drm = nouveau_bdev(bo->bdev); + struct nouveau_bo *nvbo = nouveau_bo(bo); + + mutex_lock(&drm->ttm.io_reserve_mutex); + list_del_init(&nvbo->io_reserve_lru); + mutex_unlock(&drm->ttm.io_reserve_mutex); +} + int nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, bool no_wait_gpu) @@ -675,8 +697,6 @@ nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, } man->func = &nouveau_vram_manager; - man->io_reserve_fastpath = false; - man->use_io_reserve_lru = true; } el...

...rve_lru(struct ttm_buffer_object *bo) +{ + struct nouveau_drm *drm = nouveau_bdev(bo->bdev); + struct nouveau_bo *nvbo = nouveau_bo(bo); + + mutex_lock(&drm->ttm.io_reserve_mutex); + list_del_init(&nvbo->io_reserve_lru); + mutex_unlock(&drm->ttm.io_reserve_mutex); +} + int nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, bool no_wait_gpu) @@ -888,6 +910,8 @@ nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, bool evict, if (bo->destroy != nouveau_bo_del_ttm) return; + nouveau_bo_del_io_reserve_lru(bo); + if (mem && new_reg->mem_type != TTM_P...

...ruct nouveau_drm *drm = nouveau_bdev(bo->bdev); > + struct nouveau_bo *nvbo = nouveau_bo(bo); > + > + mutex_lock(&drm->ttm.io_reserve_mutex); > + list_del_init(&nvbo->io_reserve_lru); > + mutex_unlock(&drm->ttm.io_reserve_mutex); > +} > + > int > nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, > bool no_wait_gpu) > @@ -674,8 +696,6 @@ nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, > } > > man->func = &nouveau_vram_manager; > - man->io_reserve_fastpath = false; > - man-&gt...

...rve_lru(struct ttm_buffer_object *bo) +{ + struct nouveau_drm *drm = nouveau_bdev(bo->bdev); + struct nouveau_bo *nvbo = nouveau_bo(bo); + + mutex_lock(&drm->ttm.io_reserve_mutex); + list_del_init(&nvbo->io_reserve_lru); + mutex_unlock(&drm->ttm.io_reserve_mutex); +} + int nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, bool no_wait_gpu) @@ -674,8 +696,6 @@ nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, } man->func = &nouveau_vram_manager; - man->io_reserve_fastpath = false; - man->use_io_reserve_lru = true; } el...

...am */ > - if (bo->mem.start + bo->mem.num_pages < mappable) > - return 0; > - > - > - nvbo->placement.fpfn = 0; > - nvbo->placement.lpfn = mappable; > - nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0); > - return nouveau_bo_validate(nvbo, false, false); > -} > - > -static int > nouveau_ttm_tt_populate(struct ttm_tt *ttm) > { > struct ttm_dma_tt *ttm_dma = (void *)ttm; > @@ -1524,7 +1496,6 @@ struct ttm_bo_driver nouveau_bo_driver = { > .sync_obj_flush = nouveau_bo_fence_flush, >...

...nsertions(+) > > > > diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c > > index af20fba..f4a2eb9 100644 > > --- a/drivers/gpu/drm/nouveau/nouveau_bo.c > > +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c > > @@ -411,6 +411,10 @@ nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, > > { > > int ret; > > > > + if (nvbo->bo.ttm && nvbo->bo.ttm->caching_state == tt_cached) > > You don't want to do it also for tt_wc ? > No the point of using writecombined memory for BOs is t...