Displaying 5 results from an estimated 5 matches for "nounwindt".
Did you mean:
nounwind
2012 Aug 07
2
[LLVMdev] ARM eabi calling convention
...e load is 8-byte aligned in the bit code.
My question was, assuming that arguments requiring double word alignment
have to be passed in even/odd registers, how does the backend know that %0
has to be passed in register r2 and r3?
*tail call arm_aapcscc void (i32, ...)* @foo0(i32 1, [2 x i32] %0)
nounwindt
*
It doesn't seem that ARM backend can figure out that "[2 x i32] %0" was
originally a structure consisting of a single double field. When I run llc,
it looks like "%0" is being passed in register r1 and r2.
*$ llc vararg1-main.ll -o -
ldr r0, .LCPI0_0
ldm r0, {r1,...
2012 Aug 07
0
[LLVMdev] ARM eabi calling convention
...the bit code.
>
> My question was, assuming that arguments requiring double word alignment
> have to be passed in even/odd registers, how does the backend know that %0
> has to be passed in register r2 and r3?
>
> tail call arm_aapcscc void (i32, ...)* @foo0(i32 1, [2 x i32] %0) nounwindt
>
> It doesn't seem that ARM backend can figure out that "[2 x i32] %0" was
> originally a structure consisting of a single double field. When I run llc,
> it looks like "%0" is being passed in register r1 and r2.
>
> $ llc vararg1-main.ll -o -
>
> ld...
2012 Aug 07
0
[LLVMdev] ARM eabi calling convention
On Aug 6, 2012, at 3:21 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
> When I compile this program
>
> $ cat vararg1-main.c
>
> typedef struct {
> double d;
> } S0;
>
> S0 g1;
>
> void foo0(int a, ...);
>
> int main(int argc, char **argv) {
> S0 s0 = { 2.0 };
>
> foo0(1, s0);
>
> printf("%f\n", g1.d);
>
2012 Aug 07
2
[LLVMdev] ARM eabi calling convention
...gt;> My question was, assuming that arguments requiring double word alignment
>> have to be passed in even/odd registers, how does the backend know that %0
>> has to be passed in register r2 and r3?
>>
>> tail call arm_aapcscc void (i32, ...)* @foo0(i32 1, [2 x i32] %0) nounwindt
>>
>> It doesn't seem that ARM backend can figure out that "[2 x i32] %0" was
>> originally a structure consisting of a single double field. When I run llc,
>> it looks like "%0" is being passed in register r1 and r2.
>>
>> $ llc vararg1...
2012 Aug 06
2
[LLVMdev] ARM eabi calling convention
When I compile this program
*$ cat vararg1-main.c
typedef struct {
double d;
} S0;
S0 g1;
void foo0(int a, ...);
int main(int argc, char **argv) {
S0 s0 = { 2.0 };
foo0(1, s0);
printf("%f\n", g1.d);
* * return 0;
}*
with this command,
*$ clang -target arm-none-linux-gnueabi-gcc -ccc-clang-archs armv7
-emit-llvm vararg1-main.c -S -o vararg1-main.ll -O3*
I get this