Displaying 2 results from an estimated 2 matches for "noressdtintbinop".
2008 Dec 05
2
[LLVMdev] (tablegen) Machine instruction without result
...ehow the no-result aspect has not been properly modelized. Therefore, I suspect my tablegen description of this instruction to be erroneous, so I paste it below with comments what I think I am doing:
//define an instruction profile with zero results,
//2 inputs which are of the same type (int)
def NOResSDTIntBinOp : SDTypeProfile<0, 2, [
SDTCisSameAs<0, 1>, SDTCisInt<0>
]>;
//define a node using that profile with a OutFlag
//property (which is a way to modelise e.g. HW internal CC registers?)
def MYcmpicc : SDNode<"MYISD::CMPICC", NOResSDTIntBinOp, [SDNPOutFlag]>;
//de...
2008 Dec 05
0
[LLVMdev] (tablegen) Machine instruction without result
...roperly modelized.
> Therefore, I suspect my tablegen description of this instruction to
> be erroneous, so I paste it below with comments what I think I am
> doing:
>
> //define an instruction profile with zero results,
> //2 inputs which are of the same type (int)
> def NOResSDTIntBinOp : SDTypeProfile<0, 2, [
> SDTCisSameAs<0, 1>, SDTCisInt<0>
> ]>;
>
> //define a node using that profile with a OutFlag
> //property (which is a way to modelise e.g. HW internal CC registers?)
> def MYcmpicc : SDNode<"MYISD::CMPICC", NOResSDTIntBinO...