Displaying 20 results from an estimated 20 matches for "noreorder".
2012 May 09
1
[LLVMdev] Directive parsing for AsmParser
I'm trying to build a standalone assembler for Mips using AsmParser and I'm facing a problem with assembly directives. Mips assembler has following syntax for .set directive
.set reorder
or
.set noreorder
which allow/disallow assembler to change the order of instructions in the block that follows. As the implemented AsmParser requires .set directive to have the following syntax:
/// ParseDirectiveSet:
/// ::= .set identifier ',' expression
I am getting an error reported when '.set r...
2013 Feb 20
3
[LLVMdev] Is va_arg correct on Mips backend?
...h8_3.mips.s
.section .mdebug.abi32
.previous
.file "ch8_3.bc"
.text
.globl _Z5sum_iiz
.align 2
.type _Z5sum_iiz, at function
.set nomips16 # @_Z5sum_iiz
.ent _Z5sum_iiz
_Z5sum_iiz:
.cfi_startproc
.frame $sp,64,$ra
.mask 0x80000000,-4
.fmask 0x00000000,0
.set noreorder
.set nomacro
.set noat
# BB#0:
lui $2, %hi(_gp_disp)
addiu $2, $2, %lo(_gp_disp)
addiu $sp, $sp, -64
$tmp2:
.cfi_def_cfa_offset 64
sw $ra, 60($sp) # 4-byte Folded Spill
$tmp3:
.cfi_offset 31, -4
addu $gp, $2, $25
sw $7, 76($sp)
sw $6, 72($sp)
sw $5, 68($sp)
lw $3, %got(__sta...
2013 Feb 20
0
[LLVMdev] Is va_arg correct on Mips backend?
....file "ch8_3.bc"
> .text
> .globl _Z5sum_iiz
> .align 2
> .type _Z5sum_iiz, at function
> .set nomips16 # @_Z5sum_iiz
> .ent _Z5sum_iiz
> _Z5sum_iiz:
> .cfi_startproc
> .frame $sp,64,$ra
> .mask 0x80000000,-4
> .fmask 0x00000000,0
> .set noreorder
> .set nomacro
> .set noat
> # BB#0:
> lui $2, %hi(_gp_disp)
> addiu $2, $2, %lo(_gp_disp)
> addiu $sp, $sp, -64
> $tmp2:
> .cfi_def_cfa_offset 64
> sw $ra, 60($sp) # 4-byte Folded Spill
> $tmp3:
> .cfi_offset 31, -4
> addu $gp, $2, $25
> sw $7, 76(...
2011 Nov 11
4
[LLVMdev] How to get MIPS from clang + llvm ?
...essages:
/tmp/cc-9SOWh0.s:8: Error: unknown pseudo-op: `.ent'
/tmp/cc-9SOWh0.s:10: Error: unknown pseudo-op: `.frame'
/tmp/cc-9SOWh0.s:11: Error: unknown pseudo-op: `.mask'
/tmp/cc-9SOWh0.s:12: Error: unknown pseudo-op: `.fmask'
/tmp/cc-9SOWh0.s:13: Error: expected comma after "noreorder"
/tmp/cc-9SOWh0.s:14: Error: expected comma after "nomacro"
/tmp/cc-9SOWh0.s:15: Error: no such instruction: `addiu $sp,$sp,-48'
/tmp/cc-9SOWh0.s:16: Error: no such instruction: `sw $ra,44($sp)'
/tmp/cc-9SOWh0.s:17: Error: no such instruction: `sw $fp,40($sp)'
/tmp/cc-9SO...
2018 Sep 06
3
How to add Loongson ISA for Mips target?
...\000"
.text
.align 2
.globl main
.set nomips16
.set nomicromips
.ent main
.type main, @function
main:
.frame $fp,48,$31 # vars= 16, regs= 3/0, args= 0, gp= 0
.mask 0xd0000000,-8
.fmask 0x00000000,0
.set noreorder
.set nomacro
daddiu $sp,$sp,-48
gssq $31,$fp,32($sp)
sd $28,24($sp)
move $fp,$sp
lui $28,%hi(%neg(%gp_rel(main)))
daddu $28,$28,$25
daddiu $28,$28,%lo(%neg(%gp_rel(main)))
move $2,$4
sd $5,8($fp)
sll $2,$2,0...
2013 Feb 19
0
[LLVMdev] Is va_arg correct on Mips backend?
Which part of the generated code do you think is not correct? Could you be
more specific?
I compiled this program with clang and ran it on a mips board. It returns
the expected result (21).
On Tue, Feb 19, 2013 at 4:15 AM, Jonathan <gamma_chen at yahoo.com.tw> wrote:
> I check the Mips backend for the following C code fragment compile result.
> It seems not correct. Is it my
2013 Feb 19
2
[LLVMdev] Is va_arg correct on Mips backend?
I check the Mips backend for the following C code fragment compile result. It seems not correct. Is it my misunderstand or it's a bug.
//ch8_3.cpp
#include <stdarg.h>
int sum_i(int amount, ...)
{
int i = 0;
int val = 0;
int sum = 0;
va_list vl;
va_start(vl, amount);
for (i = 0; i < amount; i++)
{
val = va_arg(vl, int);
sum += val;
}
va_end(vl);
2013 Feb 04
2
[LLVMdev] Problem with PTX assembly printing (NVPTX backend)
...instance, the "mips" target produces this:
.section .mdebug.abi32
.previous
.file "helloworld.ll"
.text
.globl main
.align 2
.type main, at function
.set nomips16 # @main
.ent main
main:
.frame $sp,24,$ra
.mask 0x80000000,-4
.fmask 0x00000000,0
.set noreorder
.set nomacro
.set noat
# BB#0:
lui $2, %hi(_gp_disp)
addiu $2, $2, %lo(_gp_disp)
addiu $sp, $sp, -24
sw $ra, 20($sp) # 4-byte Folded Spill
addu $gp, $2, $25
lw $1, %got($str)($gp)
lw $25, %call16(puts)($gp)
jalr $25
addiu $4, $1, %lo($str)
addiu $2, $zero, 0
lw $ra, 20($sp)...
2012 Nov 11
2
[LLVMdev] Tracing nodes in selectionDAG to final code...
...tion-model=static -o hello.s
to produce this MIPS code:
.section .mdebug.abi32
.previous
.file "hello.bc"
.text
.globl main
.align 2
.type main, at function
.set nomips16 # @main
.ent main
main:
.cfi_startproc
.frame $sp,32,$ra
.mask 0x80000000,-4
.fmask 0x00000000,0
.set noreorder
.set nomacro
# BB#0: # %entry
addiu $sp, $sp, -32
$tmp2:
.cfi_def_cfa_offset 32
sw $ra, 28($sp) # 4-byte Folded Spill
$tmp3:
.cfi_offset 31, -4
lui $2, %hi(__gnu_local_gp)
addiu $2, $2, %lo(__gnu_local_gp)
sw $2, 16($sp)
sw $zero, 24($sp)
lui $2, %hi($.str...
2013 Oct 03
1
[LLVMdev] Help with a Microblaze code generation problem.
...ry to track the problem down I tried compiling it for the Mips (which
works, of course) for both unsigned long long and signed long long with
the following results:
unsigned long long:
main:
.frame $fp,24,$ra
.mask 0x40000000,-4
.fmask 0x00000000,0
.set noreorder
.set nomacro
.set noat
addiu $sp, $sp, -24
sw $fp, 20($sp)
move $fp, $sp
sw $zero, 16($fp)
addiu $1, $zero, 100
sw $1, 12($fp)
sw $zero, 8($fp)
lui $1, 32768
sw...
2018 Sep 06
2
How to add Loongson ISA for Mips target?
...set nomips16
>> .set nomicromips
>> .ent main
>> .type main, @function
>> main:
>> .frame $fp,48,$31 # vars= 16, regs= 3/0, args= 0, gp= 0
>> .mask 0xd0000000,-8
>> .fmask 0x00000000,0
>> .set noreorder
>> .set nomacro
>> daddiu $sp,$sp,-48
>> gssq $31,$fp,32($sp)
>> sd $28,24($sp)
>> move $fp,$sp
>> lui $28,%hi(%neg(%gp_rel(main)))
>> daddu $28,$28,$25
>> daddiu $28,$28,%lo(%neg(%gp_rel(main)))...
2014 Mar 11
4
[PATCH] add mips64 support
...move v0,a1
+ jr ra
+
+ END(longjmp)
diff --git a/usr/klibc/arch/mips64/syscall.S b/usr/klibc/arch/mips64/syscall.S
new file mode 100644
index 0000000..cca0db2
--- /dev/null
+++ b/usr/klibc/arch/mips64/syscall.S
@@ -0,0 +1,15 @@
+#include <machine/asm.h>
+#include <asm/unistd.h>
+
+ .set noreorder
+
+LEAF(__syscall_common)
+ syscall
+ beqz a3, 1f
+ # sw is actually two instructions; the first one goes
+ # in the branch delay slot
+ # XXX: Break this up manually; as it is now it generates warnings.
+ sw v0, errno
+ li v0, -1
+1: jr ra
+ END(__syscal...
2013 Feb 04
0
[LLVMdev] Problem with PTX assembly printing (NVPTX backend)
...> .globl main
> .align 2
> .type main, at function
> .set nomips16 # @main
> .ent main
> main:
> .frame $sp,24,$ra
> .mask 0x80000000,-4
> .fmask 0x00000000,0
> .set noreorder
> .set nomacro
> .set noat
> # BB#0:
> lui $2, %hi(_gp_disp)
> addiu $2, $2, %lo(_gp_disp)
> addiu $sp, $sp, -24
> sw $ra, 20($sp) # 4-byte Folded Spill
> addu $gp, $2, $25
>...
2006 Jun 26
2
[klibc 28/43] mips support for klibc
...+ END(longjmp)
diff --git a/usr/klibc/arch/mips/syscall.S b/usr/klibc/arch/mips/syscall.S
new file mode 100644
index 0000000..9f308df
--- /dev/null
+++ b/usr/klibc/arch/mips/syscall.S
@@ -0,0 +1,16 @@
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/unistd.h>
+
+ .set noreorder
+
+LEAF(__syscall_common)
+ syscall
+ beqz a3, 1f
+ # sw is actually two instructions; the first one goes
+ # in the branch delay slot
+ # XXX: Break this up manually; as it is now it generates warnings.
+ sw v0, errno
+ li v0, -1
+1: jr ra
+ END(__syscal...
2004 Aug 06
1
status report on the Windows CE (PocketPC) ACM codec
>
> It was essentially my own mistake. After the Embedded C++ IDE crashed
unexpectedly,
> the .lib file was no longer present in the project settings (the project
had not been saved)
> so all the errors I got were caused by a missing .lib reference in the
link stage!
> I had to change my cross compiler target to "arm-wince-pe" because
otherwise the
> object/.lib files
2012 Dec 28
1
[LLVMdev] [PATCH] LLVM build failure on OpenBSD/mips64
...1 @@
".globl " ASMPREFIX "MipsCompilationCallback\n"
ASMPREFIX "MipsCompilationCallback:\n"
".ent " ASMPREFIX "MipsCompilationCallback\n"
- ".frame $sp, 32, $ra\n"
+ ".frame $29, 32, $31\n"
".set noreorder\n"
- ".cpload $t9\n"
+ ".cpload $25\n"
- "addiu $sp, $sp, -64\n"
+ "addiu $29, $29, -64\n"
".cprestore 16\n"
// Save argument registers a0, a1, a2, a3, f12, f14 since they may contain
@@ -115,35 +115,35 @@
// conc...
2013 Feb 04
0
[LLVMdev] Problem with PTX assembly printing (NVPTX backend)
On Mon, Feb 4, 2013 at 1:09 PM, <nkavv at physics.auth.gr> wrote:
> Hi Justin,
>
>
> Has anyone had similar problems with the NVPTX backend? Shouldn't this
>>> code be linked to the AsmPrinter library for NVPTX (already)?
>>>
>>
>> What do you mean by "doesn't work"? The AsmPrinter library really houses
>> the MCInst
2013 Feb 04
3
[LLVMdev] Problem with PTX assembly printing (NVPTX backend)
Hi Justin,
>> Has anyone had similar problems with the NVPTX backend? Shouldn't this
>> code be linked to the AsmPrinter library for NVPTX (already)?
>
> What do you mean by "doesn't work"? The AsmPrinter library really houses
> the MCInst printer, which isn't implemented for NVPTX yet. The older
> assembly printer works just fine. This is
2019 Jan 18
0
[klibc:master] Add RISC-V (RV64) port
...$$$$@) {
my($outputdir, $fname, $type, $sname, $stype, @args) = @_;
@@ -17,12 +16,10 @@ sub make_sysstub($$$$$@) {
print OUT "#include <machine/asm.h>\n";
print OUT "#include <asm/unistd.h>\n";
print OUT "\n";
- print OUT "\t.set noreorder\n";
- print OUT "\n";
- print OUT "LEAF(${fname})\n";
+ print OUT "ENTRY(${fname})\n";
+ print OUT "\tli\ta7, __NR_${sname}\n";
print OUT "\tj\t__syscall_${stype}\n";
- print OUT "\t li\tv0, __NR_${sname}\n";
-...
2006 Jun 28
35
[klibc 00/31] klibc as a historyless patchset (updated and reorganized)
I have updated the klibc patchset based on feedback received. In
particular, the patchset has been reorganized so as not to break
git-bisect.
Additionally, this updates the patch base to 2.6.17-git12
(d38b69689c349f35502b92e20dafb30c62d49d63) and klibc 1.4.8; the main
difference on the klibc side is removal of obsolete code.
This is also available as a git tree at: