search for: nophi

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2019 Sep 09
2
LiveInterval error with 2 dead defs
...nstrs -run-pass=machine-scheduler -o - -verify-misched foo.mir # Before machine scheduling. ********** INTERVALS ********** %0 [16r,16d:1)[32r,32d:0) 0 at 32r 1 at 16r weight:0.000000e+00 RegMasks: ********** MACHINEINSTRS ********** # Machine code for function multiple_connected_components_dead: NoPHIs, TracksLiveness 0B bb.0: 16B dead %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec 32B dead %0:vgpr_32 = V_MOV_B32_e32 1, implicit $exec # End machine code for function multiple_connected_components_dead. *** Bad machine code: Multiple connected components in live interv...
2017 Jul 27
2
Tail merging "undef" with a defined register: wrong code
...the code would still behave the same as the original. At the same time, any subsequent optimization may "exploit" the incorrect liveness information to do something bad. If you add -run-pass if-converter, you'll get: # After If Converter # Machine code for function fred: IsSSA, NoPHIs, TracksLiveness, NoVRegs BB#0: %R0<def> = L2_ploadruhf_io %P0<undef>, %R0<undef>, 0, %R0<imp-use> PS_storerhabs 0, %R0 PS_jmpret %R31<kill>, %PC<imp-def> # End machine code for function fred. *** Bad machine code: Using an undefined...
2019 Feb 13
2
Question about register allocation
Hi, I'd like to understand how register allocation works in the case where an instruction is folded into another one. Where in the code would be a good place to start looking at? After ISEL, one of the instructions has another instruction folded into it, which looks like this t1: i32,i1,i1,i1,i1 = ADDRR TargetFrameIndex:i32<0>, MOVRI:i32,i1,i1 But during the 'Assembly
2017 Oct 31
2
Reaching definitions on Machine IR post register allocation
...ch either goes to the side block (BB#1), or > to the join block (BB#2). The register R0 is defined in BB#0 and then > redefined in BB#1. Both definitions can reach the use of R0 in BB#2: > > > *** > Before Hexagon RDF optimizations > # Machine code for function fred: IsSSA, NoPHIs, TracksLiveness, NoVRegs > > BB#0: >     Live Ins: %P0 >         %R0<def> = IMPLICIT_DEF >         J2_jumpt %P0, <BB#2>, %PC<imp-def>  ; Conditional branch to BB#2 >     Successors according to CFG: BB#1 BB#2 > > BB#1: >     Predecessors accordin...
2017 Jul 28
2
Tail merging "undef" with a defined register: wrong code
...ehave the same as the original. At the same time, any subsequent optimization may "exploit" the incorrect liveness information to do something bad. If you add -run-pass if-converter, you'll get: >> >> # After If Converter >> # Machine code for function fred: IsSSA, NoPHIs, TracksLiveness, NoVRegs >> >> BB#0: >> %R0<def> = L2_ploadruhf_io %P0<undef>, %R0<undef>, 0, %R0<imp-use> >> PS_storerhabs 0, %R0 >> PS_jmpret %R31<kill>, %PC<imp-def> >> >> # End machine code fo...
2018 Sep 11
2
linear-scan RA
...> ********** INTERVALS ********** > %0 [16r,64B:0)[112B,144r:0) 0 at 16r weight:0.000000e+00 > %1 [80r,112B:1)[144r,176B:0)[176B,192r:2) 0 at 144r 1 at 80r 2 at 176B-phi weight:0.000000e+00 > RegMasks: > ********** MACHINEINSTRS ********** > # Machine code for function somefunc: NoPHIs > > 0B bb.0: > successors: %bb.2(0x80000000); %bb.2(100.00%) > > 16B %0:gr32 = MOV32ri 42 > 32B JB_1 %bb.2, implicit undef $eflags > 48B JMP_1 %bb.2 > > 64B bb.1: > successors: %bb.3(0x80000000); %bb.3(100.00%) > > 80B %1:gr32 = MOV32ri 17 >...
2017 Sep 12
6
Reaching definitions on Machine IR post register allocation
Hi Venu, > On Sep 11, 2017, at 11:00 PM, Raghavan, Venugopal via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi Krzysztof, > > Thanks for your reply. > > I agree that adding extra register units for x86 would be the right way to fix this. Do you know if there is a plan to fix this? No concrete plan, no. We've been thinking about for quite some time now, but
2017 Nov 01
2
Reaching definitions on Machine IR post register allocation
...ch either goes to the side block > (BB#1), or to the join block (BB#2). The register R0 is defined in > BB#0 and then redefined in BB#1. Both definitions can reach the use of R0 in BB#2: > > > *** > Before Hexagon RDF optimizations > # Machine code for function fred: IsSSA, NoPHIs, TracksLiveness, > NoVRegs > > BB#0: >     Live Ins: %P0 >         %R0<def> = IMPLICIT_DEF >         J2_jumpt %P0, <BB#2>, %PC<imp-def>  ; Conditional branch to > BB#2 >     Successors according to CFG: BB#1 BB#2 > > BB#1: >     Predecess...
2018 Sep 11
2
linear-scan RA
...****** > > %0 [16r,64B:0)[112B,144r:0) 0 at 16r weight:0.000000e+00 > > %1 [80r,112B:1)[144r,176B:0)[176B,192r:2) 0 at 144r 1 at 80r 2 at 176B-phi > weight:0.000000e+00 > > RegMasks: > > ********** MACHINEINSTRS ********** > > # Machine code for function somefunc: NoPHIs > > > > 0B bb.0: > > successors: %bb.2(0x80000000); %bb.2(100.00%) > > > > 16B %0:gr32 = MOV32ri 42 > > 32B JB_1 %bb.2, implicit undef $eflags > > 48B JMP_1 %bb.2 > > > > 64B bb.1: > > successors: %bb.3(0x80000000); %bb.3(100.00%) &g...
2018 Sep 11
2
linear-scan RA
The phi instruction is irrelevant; just the way I think about things. The question is if the allocator believes that t0 and t2 interfere. Perhaps the coalescing example was too simple. In the general case, we can't coalesce without a notion of interference. My worry is that looking at interference by ranges of instruction numbers leads to inaccuracies when a range is introduced by a copy.
2019 Oct 07
2
LiveInterval error with 2 dead defs
...nstrs -run-pass=machine-scheduler -o - -verify-misched foo.mir # Before machine scheduling. ********** INTERVALS ********** %0 [16r,16d:1)[32r,32d:0) 0 at 32r 1 at 16r weight:0.000000e+00 RegMasks: ********** MACHINEINSTRS ********** # Machine code for function multiple_connected_components_dead: NoPHIs, TracksLiveness 0B bb.0: 16B dead %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec 32B dead %0:vgpr_32 = V_MOV_B32_e32 1, implicit $exec # End machine code for function multiple_connected_components_dead. *** Bad machine code: Multiple connected components in live interv...
2017 Jul 27
2
Tail merging "undef" with a defined register: wrong code
The comment in test/CodeGen/X86/branchfolding-undef.mir states that such merging is legal, however doing so can actually generate wrong code: Consider this (valid code): --- name: fred tracksRegLiveness: true body: | bb.0: successors: %bb.1, %bb.2 J2_jumpt undef %p0, %bb.2, implicit-def %pc J2_jump %bb.1, implicit-def %pc bb.1: successors: %bb.3 %r0 =
2017 Nov 13
2
Reaching definitions on Machine IR post register allocation
...), or to the join block (BB#2). The register R0 is defined in > BB#0 and then redefined in BB#1. Both definitions can reach the > use of R0 in BB#2: > > > *** > Before Hexagon RDF optimizations > # Machine code for function fred: IsSSA, NoPHIs, TracksLiveness, > NoVRegs > > BB#0: >       Live Ins: %P0 >           %R0<def> = IMPLICIT_DEF >           J2_jumpt %P0, <BB#2>, %PC<imp-def>  ; Conditional > branch to > BB#2 >      ...
2018 Sep 11
2
linear-scan RA
...,144r:0) 0 at 16r weight:0.000000e+00 > >> > %1 [80r,112B:1)[144r,176B:0)[176B,192r:2) 0 at 144r 1 at 80r 2 at 176B-phi > weight:0.000000e+00 > >> > RegMasks: > >> > ********** MACHINEINSTRS ********** > >> > # Machine code for function somefunc: NoPHIs > >> > > >> > 0B bb.0: > >> > successors: %bb.2(0x80000000); %bb.2(100.00%) > >> > > >> > 16B %0:gr32 = MOV32ri 42 > >> > 32B JB_1 %bb.2, implicit undef $eflags > >> > 48B JMP_1 %bb.2 > >> > > &g...
2017 Nov 24
2
Reaching definitions on Machine IR post register allocation
...> in >>> BB#0 and then redefined in BB#1. Both definitions can reach the >>> use of R0 in BB#2: >>> >>> >>> *** >>> Before Hexagon RDF optimizations >>> # Machine code for function fred: IsSSA, NoPHIs, TracksLiveness, >>> NoVRegs >>> >>> BB#0: >>> Live Ins: %P0 >>> %R0<def> = IMPLICIT_DEF >>> J2_jumpt %P0, <BB#2>, %PC<imp-def> ; Conditional >>>...
2020 Mar 31
2
[ARM] Register pressure with -mthumb forces register reload before each call
...t 128r %0 [48r,288r:0) 0 at 48r weight:0.000000e+00 %1 [32r,304r:0) 0 at 32r weight:0.000000e+00 %2 [16r,320r:0) 0 at 16r weight:0.000000e+00 %3 [80r,336r:0) 0 at 80r weight:0.000000e+00 RegMasks: 144r 240r 336r ********** MACHINEINSTRS ********** # Machine code for function uECC_shared_secret: NoPHIs, TracksLiveness Constant Pool: cp#0: @foo, align=4 Function Live Ins: $r0 in %0, $r1 in %1, $r2 in %2 0B bb.0.entry: liveins: $r0, $r1, $r2 16B %2:tgpr = COPY $r2 32B %1:tgpr = COPY $r1 48B %0:tgpr = COPY $r0 64B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp...
2018 Sep 11
2
linear-scan RA
...weight:0.000000e+00 >>>>>> %1 [80r,112B:1)[144r,176B:0)[176B,192r:2) 0 at 144r 1 at 80r 2 at 176B-phi weight:0.000000e+00 >>>>>> RegMasks: >>>>>> ********** MACHINEINSTRS ********** >>>>>> # Machine code for function somefunc: NoPHIs >>>>>> >>>>>> 0B bb.0: >>>>>> successors: %bb.2(0x80000000); %bb.2(100.00%) >>>>>> >>>>>> 16B %0:gr32 = MOV32ri 42 >>>>>> 32B JB_1 %bb.2, implicit undef $eflags >>>>>>...
2020 Apr 07
2
[ARM] Register pressure with -mthumb forces register reload before each call
If I'm understanding what's going on in this test correctly, what's happening is: * ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize * In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6) * The function has three arguments, so those three plus the register we need to hold the
2020 Apr 15
4
[ARM] Register pressure with -mthumb forces register reload before each call
...at 224r 4 at 128r %0 [48r,416r:0) 0 at 48r weight:0.000000e+00 %1 [32r,400r:0) 0 at 32r weight:0.000000e+00 %2 [16r,320r:0) 0 at 16r weight:0.000000e+00 %3 [80r,432r:0) 0 at 80r weight:0.000000e+00 RegMasks: 144r 240r 336r 432r ********** MACHINEINSTRS ********** # Machine code for function f: NoPHIs, TracksLiveness Constant Pool: cp#0: @bar, align=4 Function Live Ins: $r0 in %0, $r1 in %1, $r2 in %2 0B bb.0.entry: liveins: $r0, $r1, $r2 16B %2:tgpr = COPY $r2 32B %1:tgpr = COPY $r1 48B %0:tgpr = COPY $r0 64B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp...