search for: nonbranchslot

...} } But that didn't seem to work. When I looked at the debug output the latency for the load instruction was set to 1. However when I changed load itinerary description in the schedule to def MyTargetItineraries : .............. InstrItinData<LD, [InstrStage<2, [BranchSlot, NonBranchSlot], 1>]>, .............. That seem to produce correct latency in the debug output. Do you know what could be the problem? Am I missing something? To give you a full disclosure, I'm using LLVM 3.5 and at the moment I can't switch to the latest version. Any help is appreciated. -...

I'm unclear how does DFAPacketizer and the scheduler know a given instruction is a load. Here is what I'm talking about Let's assume my VLIW target is described as follows: def MyTargetItineraries : ProcessorItineraries<[Slot0, Slot1], [], [ .............................. InstrItinData<RI, [InstrStage<1, [Slot0, Slot1]>]>,

...debug output the >> latency for the load instruction was set to 1. >> >> However when I changed load itinerary description in the schedule to >> >> def MyTargetItineraries : >> .............. >> InstrItinData<LD, [InstrStage<2, [BranchSlot, NonBranchSlot], 1>]>, >> .............. >> >> That seem to produce correct latency in the debug output. >> >> Do you know what could be the problem? Am I missing something? To give >> you a full disclosure, I'm using LLVM 3.5 and at the moment I can't >&g...