Displaying 7 results from an estimated 7 matches for "nonaliasing".
2015 Jan 30
2
[LLVMdev] [PATCH] Bugfix for missed dependency from store to load in buildSchedGraph().
...of previous mem uses, mapped to the same Value, is afterwards cleared
(regardless of ThisMayAlias). This means that during handling of the
next store using the same Value, adjustChainDeps() must be called,
otherwise a dependency might be missed.
For example, three spill/reload (NonAliasing) memory accesses using
the same Value 'a', with different offsets:
SU(2): store @a
SU(1): store @a, Offset:1
SU(0): load @a
In this case we have:
* SU(1) does not need a dep against SU(0). Therefore,SU(0) ends up in
RejectMemNodes and is remo...
2015 Feb 10
2
[LLVMdev] [PATCH] Bugfix for missed dependency from store to load in buildSchedGraph().
...ched patches). Basically, when an SU's underlying
objects are analyzed, the results are remembered by putting the SU into one or both of the (added)
sets AliasMemUseDefMIs and NonAliasMemUseDefMIs. Later, MIsNeedChainEdge() can return
false, if they were originally in different domains:
// A NonAliasing node cannot alias an AliasingNode. This is the case
// where MIa had only non-aliasing underlying objects and MIb had
// only aliasing underlying objects, or vice versa.
if ((AliasMemUseDefMIs.count(MIa) && !NonAliasMemUseDefMIs.count(MIa) &&
!AliasMemUseDefMIs.count(MI...
2016 Feb 22
2
Re: Cubietruck: QEMU, KVM and Fedora
...with KVM module enabled?
> With more current QEMU -cpu [ -machine ] still is valid ?
>
> Thanks,
>
> Thomas
>
>
> root@cubietruck:~# dmesg | grep CPU
> [ 0.000000] CPU: ARMv7 Processor [410fc074] revision 4 (ARMv7),
> cr=30c5387d
> [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing
> instruction cache
> [ 0.000000] PERCPU: Embedded 12 pages/cpu @ee5c0000 s19916 r8192 d21044
> u49152
> [ 0.000000] RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
> [ 0.004932] CPU: Testing write buffer coherency: ok
> [ 0.046656] CPU0...
2018 Jan 25
0
Problems getting nouveau to work with either Geforce GT710 or Geforce 9800GT on ARM Cortex-A9
...n physical CPU 0x0
[ 0.000000] Linux version 4.15.0-rc8-next2g-gfd920f6-dirty (lpnm at ENIAC10) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #2 SMP Thu Jan 25 12:44:50 WET 2018
[ 0.000000] CPU: ARMv7 Processor [414fc091] revision 1 (ARMv7), cr=10c5387d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] Memory policy: Data cache writealloc
[ 0.000000] random: fast init done
[ 0.000000] percpu: Embedded 16 pages/cpu @(ptrval) s35212 r8192 d22132 u65536
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 260096
[ 0...
2018 Jan 23
2
Problems getting nouveau to work with either Geforce GT710 or Geforce 9800GT on ARM Cortex-A9
...n physical CPU 0x0
[ 0.000000] Linux version 4.15.0-rc4-next2g-g400b6af-dirty (lpnm at ENIAC10) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #2 SMP Sun Jan 21 11:08:49 WET 2018
[ 0.000000] CPU: ARMv7 Processor [414fc091] revision 1 (ARMv7), cr=10c5387d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] Memory policy: Data cache writealloc
[ 0.000000] random: fast init done
[ 0.000000] percpu: Embedded 16 pages/cpu @(ptrval) s35148 r8192 d22196 u65536
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 260096
[ 0...
2012 Mar 19
24
[PATCHv2 00/11] arm: pass a device tree to dom0
This series of patches makes Xen pass a (somewhat) valid device tree
to dom0. The device tree for dom0 is the same as the one supplied to
Xen except the memory and chosen nodes are adjusted appropriately.
We don''t yet make use of the device tree to map MMIO regions or setup
interrupts for the guest and we still include the UART used for Xen''s
console.
Note that loading Linux
2018 Jan 25
2
Problems getting nouveau to work with either Geforce GT710 or Geforce 9800GT on ARM Cortex-A9
Hi Ben,
Thanks for your reply.
My replies follow in between.
Luís
On Thu, Jan 25, 2018 at 5:40 AM, Ben Skeggs <skeggsb at gmail.com> wrote:
> On 24 January 2018 at 06:19, Luís Mendes <luis.p.mendes at gmail.com> wrote:
>> Hi Arnd,
>>
>> Sorry for sending this email directly to you, but maybe you can help
>> me, or guide me where to look for.
>>