search for: nomips16

...91&r1=176990&r2=176991&view=diff > ============================================================================== > --- cfe/trunk/test/CodeGen/mips16-attr.c (original) > +++ cfe/trunk/test/CodeGen/mips16-attr.c Wed Mar 13 17:44:19 2013 > @@ -11,7 +11,7 @@ void __attribute__((nomips16)) nofoo (vo > > // CHECK: define void @nofoo() [[NOMIPS16:#[0-9]+]] > > -// CHECK: attributes [[MIPS16]] = { nounwind "mips16" {{.*}} } > +// CHECK: attributes [[MIPS16]] = { nounwind {{.*}} "mips16" {{.*}} } > > -// CHECK: attributes [[NOMIPS16]] = { nou...

Yes, you could have mips16 and fastcc. Mips16 just means that processor mode to execute that function is "mips16". So in a mips16 designated function, I will just emit mips16 instructions and in a "nomips16" function, just emit normal mips32 instructions. I tend to call this "mips32" normal mode, "standard encoding" because in reality the processor is mips32 for both "mips16" and "nomips16". Nomips16 means normal "mips32" mode at this time. (We...

...rove the checkin. On 01/11/2013 07:35 AM, Reed Kotler wrote: > Yes, you could have mips16 and fastcc. > > Mips16 just means that processor mode to execute that function is "mips16". > So in a mips16 designated function, I will just emit mips16 instructions > and in a "nomips16" > function, just emit normal mips32 instructions. > > I tend to call this "mips32" normal mode, "standard encoding" because in > reality the processor is > mips32 for both "mips16" and "nomips16". > > Nomips16 means normal "mip...

...add another register class for Mips16 and don't want to define a Mips16 set of registers because in reality there is no such thing; MIPS16 is an application extension that can exist for either Mips32 or Mips64 which uses a different instruction encoding. When I'm compiling for -mips23 -nomips16 I don't want the mips16 register class being passed to any functions which take such a register class parameter. As it is right now, it sees mips16 as the minimal size class and passes it when I'm compiling for -mips32 -nomips16

...o add two of the mips32 register sets (including float point which should have a big effect on things) and then computeRegisterProperties() and then revert things to mips16 only registers and call computeRegisterProperties() again. I have several more patches I will need to complete this mips16/nomips16 feature but it's easier to do this in pieces. In the end I will remove this testing code from lib/Target/Mips/Mips16ISelLowering.cpp and create a real test case for this. For now this test code shows how this feature can work for other ports like Arm than have a similar need. -------------...

...other register class for Mips16 and don't want to define a Mips16 set of registers because in reality there is no such thing; MIPS16 is an application extension that can exist for either Mips32 or Mips64 which uses a different instruction encoding. > > When I'm compiling for -mips23 -nomips16 I don't want the mips16 register class being passed to any functions which take such a register class parameter. > > As it is right now, it sees mips16 as the minimal size class and passes it when I'm compiling for -mips32 -nomips16 The ARM tGPR register class is the same. It has no...

For target dependent function level attributes, do I need to actually add them to the enumeration in attributes.h? I have for example, mips16 and nomips16 as attributes. Or is this supposed to be done with cc <n>

...egister class for Mips16 and don't want to define a Mips16 set of registers because in reality there is no such thing; MIPS16 is an application extension that can exist for either Mips32 or Mips64 which uses a different instruction encoding. >> >> When I'm compiling for -mips23 -nomips16 I don't want the mips16 register class being passed to any functions which take such a register class parameter. >> >> As it is right now, it sees mips16 as the minimal size class and passes it when I'm compiling for -mips32 -nomips16 > The ARM tGPR register class is the same...

...actually part of the function calling convention. On Fri, Jan 11, 2013 at 12:20 AM, reed kotler <rkotler at mips.com> wrote: > For target dependent function level attributes, do I need to actually add > them to the enumeration in attributes.h? > > I have for example, mips16 and nomips16 as attributes. > > Or is this supposed to be done with cc <n> > > > > > > > ______________________________**_________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/**mailman/listin...

...lass for Mips16 and don't want to define a Mips16 set of registers because in reality there is no such thing; MIPS16 is an application extension that can exist for either Mips32 or Mips64 which uses a different instruction encoding. >>> >>> When I'm compiling for -mips23 -nomips16 I don't want the mips16 register class being passed to any functions which take such a register class parameter. >>> >>> As it is right now, it sees mips16 as the minimal size class and passes it when I'm compiling for -mips32 -nomips16 >> The ARM tGPR register clas...

...linker/loader, then it maybe is correct. clang -c ch8_3.cpp -emit-llvm -o ch8_3.bc llc -march=mips -relocation-model=pic -filetype=asm ch8_3.bc -o ch8_3.mips.s .section .mdebug.abi32 .previous .file "ch8_3.bc" .text .globl _Z5sum_iiz .align 2 .type _Z5sum_iiz, at function .set nomips16 # @_Z5sum_iiz .ent _Z5sum_iiz _Z5sum_iiz: .cfi_startproc .frame $sp,64,$ra .mask 0x80000000,-4 .fmask 0x00000000,0 .set noreorder .set nomacro .set noat # BB#0: lui $2, %hi(_gp_disp) addiu $2, $2, %lo(_gp_disp) addiu $sp, $sp, -64 $tmp2: .cfi_def_cfa_offset 64 sw $ra, 6...

...ang -c ch8_3.cpp -emit-llvm -o ch8_3.bc > llc -march=mips -relocation-model=pic -filetype=asm ch8_3.bc -o > ch8_3.mips.s > > .section .mdebug.abi32 > .previous > .file "ch8_3.bc" > .text > .globl _Z5sum_iiz > .align 2 > .type _Z5sum_iiz, at function > .set nomips16 # @_Z5sum_iiz > .ent _Z5sum_iiz > _Z5sum_iiz: > .cfi_startproc > .frame $sp,64,$ra > .mask 0x80000000,-4 > .fmask 0x00000000,0 > .set noreorder > .set nomacro > .set noat > # BB#0: > lui $2, %hi(_gp_disp) > addiu $2, $2, %lo(_gp_disp) > addiu $s...

How is alignment set? On 02/04/2014 08:48 AM, Rafael Espíndola wrote: > On 31 January 2014 18:59, reed kotler <rkotler at mips.com> wrote: >> I'm rewriting this patch for the stubs to not use outputing of raw text. >> >> Generating the instructions is very straightforward and that part is done. > awesome! > >> I'm translating the actual function

...quot;git grep '\.align'"). > > Cheers, > Rafael Not on a symbol but in a section to set the current value. I have not found it so far but am looking where this can be in AsmPrinter or MC. I have these statements left to translate. Most we already discussed. .align 2 the .nomips16 and .nomicromips we have it in mipsTargetStreamer (which to me seems little different from emit raw text). I think you mentioned already how to do the .size OutStreamer.EmitRawText(".align 2"); OutStreamer.EmitRawText(".nomips16"); OutStreamer.EmitRawText(".nomi...

On May 14, 2012, at 1:02 PM, reed kotler wrote: > Does anyone understand the purpose of : > > TargetRegisterInfo::getMinimalPhysRegClass ??? Barely. > Why is there the presumption to use the minimal subclass? The function can be traced back to a time when men were men and registers belonged to ONE register class. That concept doesn't make sense any longer, as LLVM supports and

...ello.c $ cat hello.s .file 1 "hello.c" .section .mdebug.abi64 .previous .nan legacy .gnu_attribute 4, 1 .abicalls .rdata .align 3 .LC0: .ascii "Hello World\000" .text .align 2 .globl main .set nomips16 .set nomicromips .ent main .type main, @function main: .frame $fp,48,$31 # vars= 16, regs= 3/0, args= 0, gp= 0 .mask 0xd0000000,-8 .fmask 0x00000000,0 .set noreorder .set nomacro daddiu $sp,$sp,-48 gssq $31,$fp,3...

Does anyone understand the purpose of : TargetRegisterInfo::getMinimalPhysRegClass ??? Why is there the presumption to use the minimal subclass? For Mips, it would work for me if we changed this to a virtual function and then I could override this to have it chose the proper register class based on the processor. I want to introduct a different register class for MIPS 16 but don't want

..." " + Twine(Symbol) + " (" + Twine(Parms) + ")"); OutStreamer.EmitRawText("\t.section\t.mips16.call.fp"+Twine(Symbol)+",\"ax\", at progbits"); OutStreamer.EmitRawText(".align 2"); OutStreamer.EmitRawText(".nomips16"); OutStreamer.EmitRawText(".nomicromips"); OutStreamer.EmitRawText("\t.ent\t__call_stub_fp_" + Twine(Symbol)); OutStreamer.EmitRawText("\t.type\t__call_stub_fp_" + Twine(Symbol) + ", @function"); OutStreamer.EmitRawText("\t__call_stub_...

...sh what I have thus far. I will probably push my changes sometime next week after more testing and cleanup. I will be putting this createNoTargetTransformationInfoPass on a mips specific switch for now. In gcc, they actually have an option which compiles every other function as either mips16 or nomips16 as a way to test this on a large source base. I will probably add that option. My solution to all of this was surprisingly simple after I got a good handle on this problem. It would work for ARM and ARM thumb easily. It's not a very big patch but I went through many iterations and was able...

Which part of the generated code do you think is not correct? Could you be more specific? I compiled this program with clang and ran it on a mips board. It returns the expected result (21). On Tue, Feb 19, 2013 at 4:15 AM, Jonathan <gamma_chen at yahoo.com.tw> wrote: > I check the Mips backend for the following C code fragment compile result. > It seems not correct. Is it my