Displaying 10 results from an estimated 10 matches for "nomemfences".
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nomemfence
2013 Dec 05
3
[LLVMdev] Loads moving across barriers
.... If I have a memfence intrinsic, I just need
to mark it with the fence attribute, and then propogate it to its
callers. There would generally only be a few of them in any program
compared to fenceless calls. To implement this with nomemfence, I would
have to mark every function with at least 4 nomemfences, and remove them
when encountering the memfence intrinsic.
2014 Jan 04
2
[LLVMdev] Loads moving across barriers
...ll take a constant i32 parameter for the address space to be fenced. This behaves as call to a function with nomemfence set for every address space except the one specified by its constant parameter. This part might not actually be necessary (the metadata plus target intrinsics marked with whatever nomemfences are required is probably enough, but might be useful anyway).
Does this sound good?
-Matt
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2013 Dec 05
0
[LLVMdev] Loads moving across barriers
...that. If I have a memfence intrinsic, I just need to mark it with the fence attribute, and then propogate it to its callers. There would generally only be a few of them in any program compared to fenceless calls. To implement this with nomemfence, I would have to mark every function with at least 4 nomemfences, and remove them when encountering the memfence intrinsic.
Sure, but the program still needs to be correct if you skip attribute propagation.
-Andy
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2013 Dec 04
2
[LLVMdev] Loads moving across barriers
On 11/11/2013 03:13 PM, Andrew Trick wrote:
> On Nov 9, 2013, at 1:39 PM, Matt Arsenault <arsenm2 at gmail.com> wrote:
>
>> On Nov 9, 2013, at 3:14 AM, Chandler Carruth <chandlerc at google.com> wrote:
>>
>>> Perhaps you're instead trying to say that with certain address spaces "noalias" (and by inference, "restrict" at the language
2013 Dec 05
0
[LLVMdev] Loads moving across barriers
On Dec 4, 2013, at 3:33 PM, Matt Arsenault <Matthew.Arsenault at amd.com> wrote:
> On 11/11/2013 03:13 PM, Andrew Trick wrote:
>> On Nov 9, 2013, at 1:39 PM, Matt Arsenault <arsenm2 at gmail.com> wrote:
>>
>>> On Nov 9, 2013, at 3:14 AM, Chandler Carruth <chandlerc at google.com> wrote:
>>>
>>>> Perhaps you're instead trying to
2013 Dec 21
2
[LLVMdev] Loads moving across barriers
...that. If I have a memfence intrinsic, I just need to mark it with the fence attribute, and then propogate it to its callers. There would generally only be a few of them in any program compared to fenceless calls. To implement this with nomemfence, I would have to mark every function with at least 4 nomemfences, and remove them when encountering the memfence intrinsic.
>
>
> Sure, but the program still needs to be correct if you skip attribute propagation.
> -Andy
Is this a requirement for an attribute? This would be a problem for the already existing noduplicate. If a function has a call t...
2013 Dec 27
3
[LLVMdev] Loads moving across barriers
On Thu, Dec 26, 2013 at 8:54 PM, Andrew Trick <atrick at apple.com> wrote:
> Others can weigh in here. This is just my understanding. Attribute
> propagation has to be optional because we can’t assume inter-procedural
> optimization runs for correct codegen. What if the memfence resides in a
> different module?
>
> In the case of noduplicate, the only reason to propagate
2013 Nov 11
0
[LLVMdev] Loads moving across barriers
On Nov 9, 2013, at 1:39 PM, Matt Arsenault <arsenm2 at gmail.com> wrote:
> On Nov 9, 2013, at 3:14 AM, Chandler Carruth <chandlerc at google.com> wrote:
>
>>
>> Perhaps you're instead trying to say that with certain address spaces "noalias" (and by inference, "restrict" at the language level) has a different semantic model than other address
2013 Nov 09
3
[LLVMdev] Loads moving across barriers
On Nov 9, 2013, at 3:14 AM, Chandler Carruth <chandlerc at google.com> wrote:
>
> Perhaps you're instead trying to say that with certain address spaces "noalias" (and by inference, "restrict" at the language level) has a different semantic model than other address spaces? While it's less worrisome than the first interpretation, I still don't really
2014 Jun 19
6
[LLVMdev] [RFC] Add compiler scheduling barriers
Hi all,
I'm currently working on implementing ACLE extensions for ARM. There
are some memory barrier intrinsics, i.e.__dsb and __isb that require
the compiler not to reorder instructions around their corresponding
built-in intrinsics(__builtin_arm_dsb, __builtin_arm_isb), including
non-memory-access instructions.[1] This is currently not possible.
It is sometimes useful to prevent the