search for: nomacro

Displaying 15 results from an estimated 15 matches for "nomacro".

2013 Feb 20
3
[LLVMdev] Is va_arg correct on Mips backend?
...ection .mdebug.abi32 .previous .file "ch8_3.bc" .text .globl _Z5sum_iiz .align 2 .type _Z5sum_iiz, at function .set nomips16 # @_Z5sum_iiz .ent _Z5sum_iiz _Z5sum_iiz: .cfi_startproc .frame $sp,64,$ra .mask 0x80000000,-4 .fmask 0x00000000,0 .set noreorder .set nomacro .set noat # BB#0: lui $2, %hi(_gp_disp) addiu $2, $2, %lo(_gp_disp) addiu $sp, $sp, -64 $tmp2: .cfi_def_cfa_offset 64 sw $ra, 60($sp) # 4-byte Folded Spill $tmp3: .cfi_offset 31, -4 addu $gp, $2, $25 sw $7, 76($sp) sw $6, 72($sp) sw $5, 68($sp) lw $3, %got(__stack_chk_guard)(...
2013 Feb 20
0
[LLVMdev] Is va_arg correct on Mips backend?
...c" > .text > .globl _Z5sum_iiz > .align 2 > .type _Z5sum_iiz, at function > .set nomips16 # @_Z5sum_iiz > .ent _Z5sum_iiz > _Z5sum_iiz: > .cfi_startproc > .frame $sp,64,$ra > .mask 0x80000000,-4 > .fmask 0x00000000,0 > .set noreorder > .set nomacro > .set noat > # BB#0: > lui $2, %hi(_gp_disp) > addiu $2, $2, %lo(_gp_disp) > addiu $sp, $sp, -64 > $tmp2: > .cfi_def_cfa_offset 64 > sw $ra, 60($sp) # 4-byte Folded Spill > $tmp3: > .cfi_offset 31, -4 > addu $gp, $2, $25 > sw $7, 76($sp) > sw $6, 7...
2011 Nov 11
4
[LLVMdev] How to get MIPS from clang + llvm ?
...cc-9SOWh0.s:10: Error: unknown pseudo-op: `.frame' /tmp/cc-9SOWh0.s:11: Error: unknown pseudo-op: `.mask' /tmp/cc-9SOWh0.s:12: Error: unknown pseudo-op: `.fmask' /tmp/cc-9SOWh0.s:13: Error: expected comma after "noreorder" /tmp/cc-9SOWh0.s:14: Error: expected comma after "nomacro" /tmp/cc-9SOWh0.s:15: Error: no such instruction: `addiu $sp,$sp,-48' /tmp/cc-9SOWh0.s:16: Error: no such instruction: `sw $ra,44($sp)' /tmp/cc-9SOWh0.s:17: Error: no such instruction: `sw $fp,40($sp)' /tmp/cc-9SOWh0.s:18: Error: no such instruction: `addu $fp,$sp,$zero' /tmp/c...
2018 Sep 06
3
How to add Loongson ISA for Mips target?
....align 2 .globl main .set nomips16 .set nomicromips .ent main .type main, @function main: .frame $fp,48,$31 # vars= 16, regs= 3/0, args= 0, gp= 0 .mask 0xd0000000,-8 .fmask 0x00000000,0 .set noreorder .set nomacro daddiu $sp,$sp,-48 gssq $31,$fp,32($sp) sd $28,24($sp) move $fp,$sp lui $28,%hi(%neg(%gp_rel(main))) daddu $28,$28,$25 daddiu $28,$28,%lo(%neg(%gp_rel(main))) move $2,$4 sd $5,8($fp) sll $2,$2,0 sw $2,0($fp)...
2013 Feb 27
2
[LLVMdev] Mips backend 3.2 va_arg possible bug
...alue then an integer value and then again a long long so the problem is that in the test2 function there is an addiu $3, $2, 4 that causes the third long long value to be read from wrong address. mipsel.s <http://llvm.1065342.n5.nabble.com/file/n55498/mipsel.s> .set nomacro # BB#0: # %entry addiu $sp, $sp, -24 sw $ra, 20($sp) # 4-byte Folded Spill addiu $2, $sp, 56 sw $2, 16($sp) addiu $2, $2, 8 sw $2, 16($sp) lw $5, 60($sp) lw $4,...
2013 Feb 19
0
[LLVMdev] Is va_arg correct on Mips backend?
Which part of the generated code do you think is not correct? Could you be more specific? I compiled this program with clang and ran it on a mips board. It returns the expected result (21). On Tue, Feb 19, 2013 at 4:15 AM, Jonathan <gamma_chen at yahoo.com.tw> wrote: > I check the Mips backend for the following C code fragment compile result. > It seems not correct. Is it my
2013 Feb 19
2
[LLVMdev] Is va_arg correct on Mips backend?
I check the Mips backend for the following C code fragment compile result. It seems not correct. Is it my misunderstand or it's a bug. //ch8_3.cpp #include <stdarg.h> int sum_i(int amount, ...) { int i = 0; int val = 0; int sum = 0; va_list vl; va_start(vl, amount); for (i = 0; i < amount; i++) { val = va_arg(vl, int); sum += val; } va_end(vl);
2013 Feb 04
2
[LLVMdev] Problem with PTX assembly printing (NVPTX backend)
...uot;mips" target produces this: .section .mdebug.abi32 .previous .file "helloworld.ll" .text .globl main .align 2 .type main, at function .set nomips16 # @main .ent main main: .frame $sp,24,$ra .mask 0x80000000,-4 .fmask 0x00000000,0 .set noreorder .set nomacro .set noat # BB#0: lui $2, %hi(_gp_disp) addiu $2, $2, %lo(_gp_disp) addiu $sp, $sp, -24 sw $ra, 20($sp) # 4-byte Folded Spill addu $gp, $2, $25 lw $1, %got($str)($gp) lw $25, %call16(puts)($gp) jalr $25 addiu $4, $1, %lo($str) addiu $2, $zero, 0 lw $ra, 20($sp) # 4...
2012 Nov 11
2
[LLVMdev] Tracing nodes in selectionDAG to final code...
...ic -o hello.s to produce this MIPS code: .section .mdebug.abi32 .previous .file "hello.bc" .text .globl main .align 2 .type main, at function .set nomips16 # @main .ent main main: .cfi_startproc .frame $sp,32,$ra .mask 0x80000000,-4 .fmask 0x00000000,0 .set noreorder .set nomacro # BB#0: # %entry addiu $sp, $sp, -32 $tmp2: .cfi_def_cfa_offset 32 sw $ra, 28($sp) # 4-byte Folded Spill $tmp3: .cfi_offset 31, -4 lui $2, %hi(__gnu_local_gp) addiu $2, $2, %lo(__gnu_local_gp) sw $2, 16($sp) sw $zero, 24($sp) lui $2, %hi($.str) addiu $4, $...
2013 Oct 03
1
[LLVMdev] Help with a Microblaze code generation problem.
...n I tried compiling it for the Mips (which works, of course) for both unsigned long long and signed long long with the following results: unsigned long long: main: .frame $fp,24,$ra .mask 0x40000000,-4 .fmask 0x00000000,0 .set noreorder .set nomacro .set noat addiu $sp, $sp, -24 sw $fp, 20($sp) move $fp, $sp sw $zero, 16($fp) addiu $1, $zero, 100 sw $1, 12($fp) sw $zero, 8($fp) lui $1, 32768 sw $1, 0($fp) s...
2018 Sep 06
2
How to add Loongson ISA for Mips target?
...et nomicromips >> .ent main >> .type main, @function >> main: >> .frame $fp,48,$31 # vars= 16, regs= 3/0, args= 0, gp= 0 >> .mask 0xd0000000,-8 >> .fmask 0x00000000,0 >> .set noreorder >> .set nomacro >> daddiu $sp,$sp,-48 >> gssq $31,$fp,32($sp) >> sd $28,24($sp) >> move $fp,$sp >> lui $28,%hi(%neg(%gp_rel(main))) >> daddu $28,$28,$25 >> daddiu $28,$28,%lo(%neg(%gp_rel(main))) >> move $2,$4 &...
2013 Feb 04
0
[LLVMdev] Problem with PTX assembly printing (NVPTX backend)
....align 2 > .type main, at function > .set nomips16 # @main > .ent main > main: > .frame $sp,24,$ra > .mask 0x80000000,-4 > .fmask 0x00000000,0 > .set noreorder > .set nomacro > .set noat > # BB#0: > lui $2, %hi(_gp_disp) > addiu $2, $2, %lo(_gp_disp) > addiu $sp, $sp, -24 > sw $ra, 20($sp) # 4-byte Folded Spill > addu $gp, $2, $25 > lw $1, %got($str)($gp) &...
2013 Feb 28
0
[LLVMdev] Mips backend 3.2 va_arg possible bug
...t; and then again a long long > so the problem is that in the test2 function there is an addiu > $3, $2, 4 > that causes the third long long value to be read from wrong address. > mipsel.s <http://llvm.1065342.n5.nabble.com/file/n55498/mipsel.s> > > .set nomacro > # BB#0: # %entry > addiu $sp, $sp, -24 > sw $ra, 20($sp) # 4-byte Folded Spill > addiu $2, $sp, 56 > sw $2, 16($sp) > addiu $2, $2, 8 > sw $2, 16($sp) >...
2013 Feb 04
0
[LLVMdev] Problem with PTX assembly printing (NVPTX backend)
On Mon, Feb 4, 2013 at 1:09 PM, <nkavv at physics.auth.gr> wrote: > Hi Justin, > > > Has anyone had similar problems with the NVPTX backend? Shouldn't this >>> code be linked to the AsmPrinter library for NVPTX (already)? >>> >> >> What do you mean by "doesn't work"? The AsmPrinter library really houses >> the MCInst
2013 Feb 04
3
[LLVMdev] Problem with PTX assembly printing (NVPTX backend)
Hi Justin, >> Has anyone had similar problems with the NVPTX backend? Shouldn't this >> code be linked to the AsmPrinter library for NVPTX (already)? > > What do you mean by "doesn't work"? The AsmPrinter library really houses > the MCInst printer, which isn't implemented for NVPTX yet. The older > assembly printer works just fine. This is