Displaying 5 results from an estimated 5 matches for "nodetoreplace".
2010 Oct 02
1
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
...;ConstantSDNode>(Op0))
>> if (RHSCI->getAPIntValue() == 1&& Op0.hasOneUse()&&
>> Op0.getOpcode() == ISD::XOR) {
>> TheXor = Op0.getNode();
>> Equal = true;
>> }
>>
>> SDValue NodeToReplace = Trunc ? SDValue(Trunc, 0) : N1;
>>
>> EVT SetCCVT = NodeToReplace.getValueType();
>> if (LegalTypes)
>> SetCCVT = TLI.getSetCCResultType(SetCCVT);
>> SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
>>...
2010 Sep 30
4
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
...Equal = false;
if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
Op0.getOpcode() == ISD::XOR) {
TheXor = Op0.getNode();
Equal = true;
}
SDValue NodeToReplace = Trunc ? SDValue(Trunc, 0) : N1;
EVT SetCCVT = NodeToReplace.getValueType();
if (LegalTypes)
SetCCVT = TLI.getSetCCResultType(SetCCVT);
SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
SetCCVT,...
2010 Oct 01
0
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
...stantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
> if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
> Op0.getOpcode() == ISD::XOR) {
> TheXor = Op0.getNode();
> Equal = true;
> }
>
> SDValue NodeToReplace = Trunc ? SDValue(Trunc, 0) : N1;
>
> EVT SetCCVT = NodeToReplace.getValueType();
> if (LegalTypes)
> SetCCVT = TLI.getSetCCResultType(SetCCVT);
> SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
> SetCCVT,
>...
2010 Sep 29
0
[LLVMdev] comparison pattern trouble - might be a bug in LLVM 2.8?
On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote:
> On 29 Sep 2010, at 06:25, Heikki Kultala wrote:
>
>> Our architecture has 1-bit boolean predicate registers.
>>
>> I've defined comparison
>>
>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;
2010 Sep 29
1
[LLVMdev] comparison pattern trouble - might be a bug in LLVM 2.8?
On 29 Sep 2010, at 06:25, Heikki Kultala wrote:
> Our architecture has 1-bit boolean predicate registers.
>
> I've defined comparison
>
>
> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;
>
>
>
>
> But then I end up having the following bug:
>
>