Displaying 4 results from an estimated 4 matches for "no_stack_slot".
2008 May 28
3
[LLVMdev] Possible VirtRegMap Bug
...ying around with spillers and found that the SimpleSpiller fails
badly on a particular code.
The problem arises because SimpleSpiller does the test
VRM.isAssignedReg(virtReg) which is implemented as:
00183 bool isAssignedReg(unsigned virtReg) const {
00184 if (getStackSlot(virtReg) == NO_STACK_SLOT &&
00185 getReMatId(virtReg) == NO_STACK_SLOT)
00186 return true;
00187 // Split register can be assigned a physical register as well as a
00188 // stack slot or remat id.
00189 return (Virt2SplitMap[virtReg] && Virt2PhysMap[virtReg] !=
NO_PHYS_R...
2008 May 30
0
[LLVMdev] Possible VirtRegMap Bug
...at the
> SimpleSpiller fails
> badly on a particular code.
>
> The problem arises because SimpleSpiller does the test
> VRM.isAssignedReg(virtReg) which is implemented as:
>
> 00183 bool isAssignedReg(unsigned virtReg) const {
> 00184 if (getStackSlot(virtReg) == NO_STACK_SLOT &&
> 00185 getReMatId(virtReg) == NO_STACK_SLOT)
> 00186 return true;
> 00187 // Split register can be assigned a physical register as
> well as a
> 00188 // stack slot or remat id.
> 00189 return (Virt2SplitMap[virtReg] && Vir...
2014 Oct 14
2
[LLVMdev] Problem of stack slot coloring
...It seems that the relevant piece of code is in
lib/CodeGen/InlineSpiller.cpp:
>
> /// spillAll - Spill all registers remaining after rematerialization.
> void InlineSpiller::spillAll() {
> // Update LiveStacks now that we are committed to spilling.
> if (StackSlot == VirtRegMap::NO_STACK_SLOT) {
> StackSlot = VRM.assignVirt2StackSlot(Original);
> StackInt = &LSS.getOrCreateInterval(StackSlot,
MRI.getRegClass(Original));
> StackInt->getNextValue(SlotIndex(), LSS.getVNInfoAllocator());
> } else
> StackInt = &LSS.getInterval(StackSlot);
>
>...
2014 Oct 13
2
[LLVMdev] Problem of stack slot coloring
Hi,
Can anyone help me with the stack slot coloring optimization?
This corresponding file is /lib/codegen/stackslotcoloring.cpp.
It is said this optimization was for stack slot overlay for frame size
reduction, after register allocation phase.
And this transformation pass relies on the LiveStack analysis pass.
How, when checking the source code, it seems the LiveStack analysis has not
been