Displaying 6 results from an estimated 6 matches for "newopc".
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2017 Aug 26
2
Error in generating Object Code for implemented assembly vector instructions
...tor assembly
instructions.
P_256B_LOAD_DWORD R_0_R2048b_0, pword ptr [rip + b]
P_256B_LOAD_DWORD R_0_R2048b_1, pword ptr [rip + c]
P_256B_VADD R_0_R2048b_0, R_0_R2048b_1, R_0_R2048b_0
P_256B_STORE_DWORD pword ptr [rip + a], R_0_R2048b_0
I added the following lines in X86MCInstLower.cpp;
unsigned NewOpc;
switch (OutMI.getOpcode()) {
default: llvm_unreachable("Invalid opcode");
case X86::P_256B_LOAD_DWORD: NewOpc = X86::P_256B_LOAD_DWORD;
break;
case X86::P_256B_STORE_DWORD: NewOpc = X86::P_256B_STORE_DWORD;
break;
case X86::P_256B_VADD: NewOpc = X86::P...
2010 Sep 07
1
[LLVMdev] MachineMemOperand and dependence information
...n ARMLoadStoreOptimizer.cpp that creates a LDRD
instruction.
Ops.pop_back();
Ops.pop_back();
// Form the pair instruction.
if (isLd) {
MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos,
dl, TII->get(NewOpc))
.addReg(EvenReg, RegState::Define)
.addReg(OddReg, RegState::Define)
.addReg(BaseReg);
if (!isT2)
MIB.addReg(OffReg);
MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
++NumLDRDFormed;
On Tue, Sep 7, 2010...
2010 Sep 07
0
[LLVMdev] MachineMemOperand and dependence information
On Sep 7, 2010, at 10:48 AM, Akira Hatanaka wrote:
> I have two questions regarding MachineMemOperands and dependence information.
>
> Q1) I noticed that MachineMemOperands are lost when two LDRs are combined and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps.
>
> (before optimization)
> %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0;
2010 Sep 07
3
[LLVMdev] MachineMemOperand and dependence information
I have two questions regarding MachineMemOperands and dependence
information.
Q1) I noticed that MachineMemOperands are lost when two LDRs are combined
and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps.
(before optimization)
%reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0;
mem:LD4[%uglygep10]
%reg1054<def> = LDR %reg1030, %reg0, 4104, pred:14,
2007 Dec 20
2
[LLVMdev] random warnings
...ed uninitialized in this function
/Volumes/mrs5/net/llvm/llvm/lib/Target/CellSPU/SPUISelLowering.cpp: In
function ‘llvm::SDOperand LowerLOAD(llvm::SDOperand,
llvm::SelectionDAG&, const llvm::SPUSubtarget*)’:
/Volumes/mrs5/net/llvm/llvm/lib/Target/CellSPU/SPUISelLowering.cpp:
563: warning: ‘NewOpC’ may be used uninitialized in this function
2007 Dec 22
0
[LLVMdev] random warnings
...this function
> /Volumes/mrs5/net/llvm/llvm/lib/Target/CellSPU/SPUISelLowering.cpp: In
> function ‘llvm::SDOperand LowerLOAD(llvm::SDOperand,
> llvm::SelectionDAG&, const llvm::SPUSubtarget*)’:
> /Volumes/mrs5/net/llvm/llvm/lib/Target/CellSPU/SPUISelLowering.cpp:
> 563: warning: ‘NewOpC’ may be used uninitialized in this function
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